US 7,679,179 B2 · Castellation wafer level packaging of integrated circuit chips

Abstract

Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.

Claims19

Dependent claims

Castellation wafer level packages for packaging integrated circuit chips, said packages comprising:

a wafer comprising an integrated circuit chip;
a castellation contact on the chip, wherein the castellation contact is large enough to be electrically coupled to solder, anisotropic conductive film, or anisotropic conductive paste;
a material substantially around the castellation contact, wherein the material exposes at least two surfaces of the castellation contact, wherein the at least two surfaces are in different intersecting planes;
and
an active circuit area contact that is in physical contact with the material and coupled to an active circuit area of the integrated circuit chip and to at least one of the exposed surfaces of the castellation contact, wherein the castellation contact is formed in a first region of the integrated circuit chip and the active circuit area contact is formed on the integrated circuit chip outside the first region.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

11/947,986Filed 30 Nov 2007 · continuation

Priority

28 Aug 2002

Published

US 2008/0067675 A120 Mar 2008

Granted

16 Mar 2010

Term ends

Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10W 90/00
Package configurations
H10W 74/129
The semiconductor body being completely enclosed: forming a chip-scale package [CSP]
H10W 70/60
Package substrates; Interposers; Redistribution layers [RDL]: insulating or insulated package substrates; Interposers; Redistribution layers
H10W 70/65
Characterised by their interconnections: shapes or dispositions of interconnections

Family

Application10/233,149Parent of this division · filed 28 Aug 2002

Application11/031,265Parent of this division · filed 7 Jan 2005

US 6,855,572 B2Parent of this division · filed 15 Feb 2005

Application11/182,427Parent of this division · filed 14 Jul 2005

Application11/221,539Parent of this continuation · filed 7 Sep 2005

US 6,949,407 B2Parent of this division · filed 27 Sep 2005

US 7,271,027 B2Parent of this division · filed 18 Sep 2007

US 2008/0067675 A1Pre-grant publication · published 20 Mar 2008

US 7,528,477 B2Parent of this continuation

Application11/221,539Parent of this division

US 2004/0043535 A1Published application

US 2005/0130345 A1Published application

US 2006/0001142 A1Published application

US 2006/0014319 A1Published application

US 7,679,179 B2This patent

From the US filing history. Foreign family members aren’t listed.

Castellation wafer level packaging of integrated circuit chips

Life of this patent

Castellation wafer level packaging of integrated circuit chips

Life of this patent

Abstract

Claims19