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US 7,679,176 B2Granted
Semiconductor device and electronic control unit using the same
AssigneeHitachi, Ltd.
InventorsMasahiko Asano, Yasuo Akutsu, Masahide Harada, Kaoru Uchiyama, Shinichi Fujiwara, Isamu Yoshida
Life of this patent
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Abstract
A semiconductor device has a substrate with an electronic circuit, a semiconductor element provided at a first surface of the substrate and electrically connected by wire bonding to the electronic circuit, a metallic core layer electrically connected to the semiconductor element. A plurality of conductive bumps provided opposite the first surface of the substrate. A thermal hardenable resin seals at least the semiconductor element, and a metal plate is electrically connected to the metal core layer.
Claims13
A semiconductor device comprising:
- a substrate with a circuit being disposed on a first principal surface;
- a semiconductor element being provided at the first principal surface of said substrate and being electrically connected by wire bonding to said circuit for interconnection therebetween;
- a metallic core layer encased within said substrate adjacent said semiconductor element and electrically connected to said semiconductor element;
- wherein a bottom surface of said semiconductor element directly attaches to a top surface of said metallic core layer through a conductive adhesive;
- a plurality of conductive bumps provided on a second principal surface opposite to the first principal surface of said substrate;
- a thermally hardenable sealing resin for sealing at least said semiconductor element and the first principal surface side of said substrate;
- and
- a metal member provided at the second principal surface and electrically connected to said metallic core layer, wherein a top surface of said metal member directly attaches to a bottom surface of said metallic core layer through a soldering material;
- wherein said substrate has therein a through hole for penetration between the first principal surface and the second principal surface;
- wherein said through hole is directly electrically coupled to said metallic core layer wherein a first counterbore is provided at the second principal surface of said substrate and wherein said metal member is provided within said first counterbore and said first counterbore exposes a portion of the bottom surface of said metallic core layer;
- and wherein a second counterbore is provided at the first principal surface of said substrate and wherein said semiconductor element is provided within said second counterbore and said second counterbore exposes a portion of the top surface of said metallic core layer.
8 more elements
A semiconductor device comprising:
- a multilayer substrate structured by lamination of a plurality of substrates each having a circuit as disposed thereon;
- a plurality of metallic core layers as internally encased within said plurality of substrates;
- a semiconductor element at a first principal surface of said multilayer substrate provided on a substrate residing at an uppermost part of said multilayer substrate adjacent an uppermost one of the metallic core layers and electrically connected by wire bonding to said circuit for interconnection therebetween;
- wherein a bottom surface of said semiconductor element directly and electrically attaches to a top surface of said the uppermost one of the metallic core layers through a conductive adhesive;
- and
- a metal member being provided at a second principal surface opposite to the first principal surface of the multilayer substrate wherein said metal member resides at a lowermost part of said multilayer substrate and is electrically connected to a metallic core layer at the lowermost part, of said multilayer substrate;
- wherein a top surface of said metal member directly attaches to a bottom surface of said metallic core layer at the lowermost part of said multilayer substrate through a soldering material;
- wherein said multilayer substrate has therein a through hole for penetration between the first principal surface and the second principal surface;
- wherein said through hole is electrically coupled to said metallic core layer wherein a first counterbore is provided at the second principal surface of said multilayer substrate and wherein said metal member is provided within said first counterbore and said first counterbore exposes a portion of the bottom surface of said metallic core layer at the lowermost part of said multilayer substrate;
- and wherein a second counterbore is provided at the first principal surface of said multilayer substrate and wherein said semiconductor element is provided within said second counterbore and said second counterbore exposes a portion of the top surface of said the uppermost one of the metallic core layers.
7 more elements
Dependencies are inferred from the claim text.