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US 7,679,175 B2Granted
Semiconductor device including substrate and upper plate having reduced warpage
AssigneeOki Semiconductor Co., Ltd.
InventorYoshihiro Saeki
Life of this patent
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Abstract
A semiconductor device includes a lower substrate having at least one wiring pattern formed of a plurality of wirings, a semiconductor chip positioned above the lower substrate and electrically connected to the wirings, an intermediate member which seals the semiconductor chip in columnar form and substantially, and an upper plate which substantially covers a whole upper surface of the intermediate member. A thermal expansion coefficient of the upper plate and a thermal expansion coefficient of the lower substrate are set substantially identical.
Claims6
A semiconductor device comprising:
- a silicon substrate having at least one wiring pattern formed of a plurality of wirings;
- a semiconductor chip positioned above the silicon substrate and electrically connected to the wirings;
- an intermediate member which seals the semiconductor chip;
- and
- an upper plate which substantially covers a whole upper surface of the intermediate member,
- wherein a thermal expansion coefficient of the upper plate is substantially identical to a thermal expansion coefficient of the silicon substrate, and
- wherein the thermal expansion coefficient of the silicon substrate and the thermal expansion coefficient of the upper plate are less than or equal to half a thermal expansion coefficient of the intermediate member.
4 more elements
Dependencies are inferred from the claim text.