US 7,679,148 B2Granted

Semiconductor device, production method and production device thereof

AssigneeNEC Corporation

InventorsHeiji Watanabe, Hirohito Watanabe, Toru Tatsumi, Shinji Fujieda

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Abstract

The task of the present invention is to enable formation of a gate insulating film structure having a good-quality interface between a silicon oxide film and silicon in an interface between a high dielectric constant thin film and a silicon substrate to provide a semiconductor device and a semiconductor manufacturing method which are capable of improving interface electrical characteristics, which has been a longstanding task in practical use of a high dielectric constant insulating film. A metal layer deposition process and a heat treatment process which supply metal elements constituting a high dielectric constant film on a surface of a base silicon oxide film 103 allow the metal elements to be diffused into the base silicon oxide film 103 to thereby form an insulating film structure 105 as a gate insulating film, after forming the base silicon oxide film 103 on a surface of a silicon substrate 101. The insulating film structure 105 including a silicate region comprises a silicon oxide film region, a silicate region, and a metal rich region, forming a silicate structure having composition modulation in which composition of metal increases as closer to an upper portion, and the composition of silicon increases as closer to a lower portion.

Claims1

Dependent claims

A semiconductor device comprising an insulating film structure which electrically insulates a conductive region from a silicon region,

wherein said insulating film structure extends on said silicon region and under said conductive region, said insulating film structure further comprising at least one silicate region composed of a silicon oxide containing at least one metal element,
wherein said insulating film structure comprises at least one silicon oxide region composed of a silicon oxide not containing said at least one metal element, at least one metal rich region having high concentration of said at least one metal element, and said at least one silicate region which is located between said silicon oxide region and said metal rich region and has lower concentration of said at least one metal element than that of said metal rich region,
wherein said silicon oxide region is located on said silicon region, said silicate region being located on said silicon oxide region, said metal rich region being located on said silicate region,
wherein said silicate region has composition modulation in which composition of said at least one metal element increases toward a surface of the device, and the composition of silicon decreases toward the surface of the device, and
wherein a second silicate region further extends on said metal rich region, the second silicate region having composition modulation in which composition of said at least one metal element decreases upward, and the composition of silicon increases upward.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/521,311Filed 16 Jul 2003
Priority: JP 2002-20667816 Jul 2002
Published: US 2005/0233526 A120 Oct 2005
Granted: 16 Mar 2010
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10D 64/01344
On single crystalline silicon, e.g. chemical oxidation using a liquid: in a nitrogen-containing ambient, e.g. N2O oxidation
H10D 64/01306
Characterised by the conductor: the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
H10D 64/021
Manufacture or treatment: using multiple gate spacer layers, e.g. bilayered sidewall spacers
H10D 64/685
Having a compositional variation, e.g. multilayered: being perpendicular to the channel plane