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US 7,679,130 B2Granted
Deep trench isolation structures and methods of formation thereof
AssigneeInfineon Technologies AG
InventorsArmin Tilke, Danny Pak-Chum Shum, Laura Pescini, Ronald Kakoschke, Karl Robert Strenz, Martin Stiftinger
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Abstract
Deep trench isolation structures and methods of formation thereof are disclosed. Several methods of and structures for increasing the threshold voltage of a parasitic transistor formed proximate deep trench isolation structures are described, including implanting a channel stop region into the bottom surface of the deep trench isolation structures, partially filling a bottom portion of the deep trench isolation structures with an insulating material, and/or filling at least a portion of the deep trench isolation structures with a doped polysilicon material.
Claims25
A semiconductor device, comprising:
- a workpiece;
- at least two devices formed within the workpiece;
- at least one deep trench isolation structure including a top portion and a bottom portion formed within the workpiece between the at least two devices, a parasitic transistor being formed in the workpiece proximate the at least one deep trench isolation structure, the parasitic transistor having a threshold voltage;
- a thin insulating liner lining the at least one deep trench isolation structure;
- a semiconductive material filling at least the top portion of the at least one deep trench isolation structure within the thin insulating liner;
- and
- a means for increasing the threshold voltage of the parasitic transistor.
4 more elements
A semiconductor device, comprising:
- a workpiece;
- at least two devices formed within the workpiece;
- at least one deep trench isolation structure including a top portion and a bottom portion formed within the workpiece between the at least two devices, the at least one deep trench isolation structure having a bottom surface and sidewalls;
- a thin insulating liner lining the bottom surface and sidewalls of the at least one deep trench isolation structure;
- a semiconductive material filling at least the top portion of the at least one deep trench isolation structure within the thin insulating liner;
- and
- a channel stop region formed in the bottom surface of the at least one deep trench isolation structure, an insulating material disposed within the portion of a bottom of the at least one deep trench isolation structure beneath the semiconductive material, and/or a dopant implanted into or in-situ deposited together with the semiconductive material filling at least the top portion of the at least one deep trench isolation structure.
4 more elements
A semiconductor device, comprising:
- a workpiece;
- a first flash memory cell and a second flash memory cell formed within the workpiece;
- at least one deep trench isolation structure including a top portion and a bottom portion formed within the workpiece between the first flash memory cell and the second flash memory cell, a parasitic transistor being formed in the workpiece proximate the at least one deep trench isolation structure, the parasitic transistor having a threshold voltage;
- a thin insulating liner lining the at least one deep trench isolation structure;
- a semiconductive material filling at least the top portion of the at least one deep trench isolation structure within the thin insulating liner;
- and
- a channel stop region formed in the bottom surface of the at least one deep trench isolation structure, an insulating material disposed within the portion of a bottom of the at least one deep trench isolation structure beneath the semiconductive material, and/or a dopant implanted into or in-situ deposited together with the semiconductive material filling at least the top portion of the at least one deep trench isolation structure, wherein the channel stop region, the insulating material, and/or the dopant of the semiconductive material increase the threshold voltage of the parasitic transistor, and wherein the first flash memory cell and the second flash memory cell each include a source region and a drain region formed within the top surface of the workpiece, a floating gate, and a control gate.
4 more elements
A semiconductor device, comprising:
- two devices formed within a workpiece;
- a trench isolation structure including a top portion and a bottom portion formed within the workpiece between the two devices, the trench isolation structure having a bottom surface and sidewalls, wherein the workpiece comprises a triple well and wherein the trench isolation structure is formed within the triple well;
- a thin insulating liner lining the bottom surface and sidewalls of the trench isolation structure;
- a semiconductive material filling at least the top portion of the trench isolation structure within the thin insulating liner;
- and
- an insulating material filling the bottom portion of the trench isolation structure beneath the semiconductive material and within the thin insulating liner.
3 more elements
A semiconductor device, comprising:
- two devices formed within a workpiece;
- a trench isolation structure including a top portion and a bottom portion formed within the workpiece between the two devices, the trench isolation structure having a bottom surface and sidewalls, wherein the bottom surface of the trench isolation structure comprises a channel stop region formed beneath the bottom surface of the trench isolation structure and within a well, the channel stop region comprising a first dopant which is different than a second dopant of the well;
- a thin insulating liner lining the bottom surface and sidewalls of the trench isolation structure;
- a semiconductive material filling at least the top portion of the trench isolation structure within the thin insulating liner;
- and
- an insulating material filling the bottom portion of the trench isolation structure beneath the semiconductive material and within the thin insulating liner.
3 more elements
Dependencies are inferred from the claim text.