Ultra scalable high speed heterojunction vertical n-channel MISFETs and methods thereof

#This invention relates to semiconductor transistors and, more particularly, to a metal insulator semiconductor field effect transistor (MISFET) consisting of a conducting channel which has no hetero-barrier in the current flow direction and a heterojunction between the source/drain and body (bulk) of the transistor.

#Silicon MOSFET scaling has become a major challenge in the semiconductor industry. Traditional techniques start to fail in reducing certain undesirable physical effects as device dimensions shrink down to the nanometer regime. For example, anti-punchthrough (APT) or halo implantation is used to reduce the short-channel effects (SCE). However, the abrupt doping profiles are difficult to achieve due to temperature enhanced diffusion, and these highly doped channels or pocket implant regions increase junction capacitance and band-to-band tunneling. It has been shown by S. Thompson, et al., in “MOS scaling: transistor challenges for the 21st century,” Intel Technology Journal, Q3, 1998, that channel engineering can only decrease the circuit gate delay by ˜10% for a given technology, and it cannot provide channel length scaling for generation after generation that gate oxide and source/drain (S/D) junction depth scaling has provided.

#With bandgap engineering, an important degree of freedom can be provided in the device design. The growth of high-quality tensile strained Si/SiGe and compressively strained SiGe/Si heterostructures by molecular beam epitaxy (MBE), various types of chemical vapor deposition (CVD), and/or ion implantation allows incorporation of bandgap engineering concepts into a mature silicon technology.

#The invention is described in more details thereinafter relative to non-limitative embodiments and with reference to the attached drawings, wherein:

#FIG. 1 is an energy band diagram of tensile strained SiC on cubic Si.

#FIG. 2 is an energy band diagram of tensile strained Si on relaxed SiGe buffer.

#The lattice spacing of carbon, silicon and germanium are 3.567 Å, 5.431 Å and 5.646 Å, respectively. Biaxial tensile strain exists in pseudomorphic SiC on relaxed Si, or in pseudomorphic Si on relaxed SiGe or Ge substrate, which means the larger lattice spacing in the growth plane (surface) and smaller lattice spacing in the growth direction (normal to the surface) in the pseudomorphic material. On the other hand, compressive strain exists in pseudomorphic SiGe on relaxed Si, or in pseudomorphic Ge on relaxed SiGe, which means the smaller lattice spacing in the growth plane (surface) and larger lattice spacing in the growth direction (normal to the surface) in the pseudomorphic material. Adding a small amount of carbon (<1%) into compressively strained SiGe on relaxed Si can compensate and reduce the strain in SiGe. Strain changes the band structure of the strained material. Therefore, strain may affect the energy band offset, effective mass and density of states. Referring to the drawing, FIG. 1 shows the conduction band and valence band of tensile strained Si1-yCy on relaxed Si buffer layer by curves 4 and 5, respectively. In this case, electrons are confined in the tensile strained Si1-yCy which has high electron mobility, and this material system is suitable for nMOSFETs. Furthermore, FIG. 2 shows the conduction band and valence band of tensile strained silicon on relaxed silicon germanium by curves 6 and 7, respectively. Electrons are confined in the tensile strained silicon which potentially has high electron mobility, and this material system may be suitable for nMOSFETs. With the two material systems, the channel could be a surface channel or a buried quantum well channel. In FIGS. 1-2, the ordinate represents energy and the abscissa represents depth.

#FIG. 3 shows a top view of a vertical device structure disclosed in this invention. FIG. 4 shows a cross-sectional view of the first embodiment. It is a SiGe based vertical nMOSFET 9 comprising a vertical mesa, a column, a pedestal, a pillar or a fin comprising several layers, such as a source layer 14, a body layer 13, and a drain layer 12, with a channel layer 15, an insulator layer 16, and a gate electrode layer 17 on the sidewalls of the mesa, column, pedestal, pillar or fin, which may be formed by etching layers 14, 13, and 12. The device has the following structural characteristics: 1) The drain is n+-type relaxed SiGe 12; 2) The body is epitaxial p-type relaxed SiGe 13, and the doping level is adjusted to achieve the desirable threshold voltage; 3) The source is epitaxial n+-type tensile strained Si 14; 4) The channel is epitaxial tensile strained Si 15, and there is no hetero-barrier along the current flow direction shown by arrows 22 and 23. The channel layer 15 forms a heterojunction with the body 13 at the interface 8 and functions to provide band offset as shown in FIG. 2 to confine electrons in the channel 15. Typically the channel is autodoped by the adjacent layer by dopant diffusion, such that the channel region 15″ over the body 13 is p-type, and the channel regions 15′ and 15′″ over the source 14 and drain 12 are doped n-type. 5) A strained Si/SiGe heterojunction is formed between source 14 and body 13 at interface 500, and preferably, aligned with the source/body metallurgical p/n junction. The off-state current is reduced because the heterojunction functions to block electrons from entering body 13, hence reducing the off-state current by orders of magnitude. The higher the strain in one layer (source 14) of the heterojunction, the higher the energy barrier, the less the leakage current will be from the source through the body to the drain when the device is turned off (i.e., off state). 6) The gate is a conducting layer 17 overlapping the entire strained silicon channel 15 comprising regions 15′, 15″, 15′″ with an insulator 16 in between. The gate extends to or overlaps part of the source 14 and drain 12. In order to reduce the gate-to-source/gate-to-drain overlap capacitance, the gate oxide overlapping the source 14 and the drain 12 can be made thicker than the oxide overlapping the body 13; 7) The drain, source and gate electrodes 19, 20 and 21 are connected to the drain 12, source 14 and gate 17, respectively; 8) Layer 10 and buffer layer 11 function to provide a relaxed SiGe template for epitaxial growth of drain 12. Layer 10 can be part of a silicon-on-insulator (SOI) substrate. Layer 10 and 11 may also be bulk Ge, Ge-on-insulator, SiGe-on-insulator, or silicon-on-sapphire (SOS). A bonded layer of suitable lattice spacing may be provided in place of substrate 10 and buffer layer 11.

#In the case when the source/drain is phosphorus-doped, phosphorus diffusion from the source/drain into the channel and the body will tend to short the source and drain in ultra-short channel devices. Adding an epitaxial SiGeC layer 200 and 201 as shown in FIG. 5 can reduce phosphorus diffusion. This is the second embodiment of the present invention. It is a nMOSFET 24 with a similar structure to the first embodiment, except that SiGeC layers 200 and 201 are included to block phosphorus diffusion from layer 12 and 14, respectively. When silicon layer 14 is highly strained, its critical thickness is rather small. The more strain in the layer, the thinner is the critical thickness at which the stained layer starts to relax. The critical thickness is understood in the art as a thickness where defects are generated within a layer to relieve its strain so that the layer relaxes towards its natural lattice spacing. The lattice spacing is determined by the composition of the layer as well as the degree of relaxation, which is typically assumed to be 100%. For example, Ge lattice is 1.04 times the lattice spacing of silicon. A 50% Ge composition in a SiGe layer would be expected to have a lattice spacing of 1.02 times the lattice spacing of silicon. In this embodiment, a relaxed SiGe layer or poly silicon or poly SiGe layer 400 is formed on top of strained silicon layer 14, and together they form the composite source that has sufficient thickness for silicidation. Layer 400 can be as thick as desired while layer 14 has a thickness below or about the critical thickness. When the thickness of SiGeC layers 200, 201, and SiGe 400 are zero, the second embodiment falls back to the first embodiment.