CMOS inverter based logic memory

A complimentary metal-oxide-silicon (CMOS) integrated circuit (IC) device including a plurality of non-volatile logic cells formed on a substrate, each non-volatile logic cell comprising:

• a polycrystalline silicon floating gate disposed over the substrate;
• a control capacitor including:
• a first capacitor including a first portion of the floating gate and an isolated P-well region formed in the substrate below the first portion of the floating gate;
• a second capacitor including a polycrystalline silicon control gate structure located adjacent to said first portion of the floating gate,
• a non-volatile p-channel transistor including a first source region and a first drain region disposed in an N-well region formed in the substrate adjacent to a second portion of the floating gate;
• and
• a non-volatile n-channel transistor including a second source region and a second drain region disposed in a P-well region formed in the substrate adjacent to a third section of the floating gate;
• wherein the isolated P-well region of the first capacitor is electrically connected to the control gate structure, and
• wherein each non-volatile logic cell further comprises a second p-channel transistor connected between the first drain and the second drain, wherein the second p-channel transistor is disposed in the N-well region.

A complimentary metal-oxide-silicon (CMOS) integrated circuit (IC) device including a plurality of non-volatile logic cells formed on a substrate, each non-volatile logic cell comprising:

• a polycrystalline silicon floating gate disposed over the substrate;
• a polycrystalline silicon control gate structure located adjacent to a first portion of the floating gate;
• and
• an inverter including:
• a non-volatile p-channel transistor including a first source region and a first drain region disposed in an N-well region formed in the substrate adjacent to a second portion of the floating gate, and
• a non-volatile n-channel transistor including a second source region and a second drain region disposed in a P-well region formed in the substrate adjacent to a third portion of the floating gate,
• wherein said control gate structure is capacitively coupled to said first portion of the floating gate such that said control gate and said first portion of the floating gate comprise a capacitor.