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US 7,679,118 B2Granted
Vertical transistor, memory cell, device, system and method of forming same
AssigneeMicron Technology, Inc.
InventorLeonard Forbes
Life of this patent
Estimating the term…
Abstract
A memory device, system and fabrication method relating to a vertical memory cell including a semiconducting pillar extending outwardly from an integrally connected semiconductor substrate are disclosed. A first source/drain region is formed in the substrate and a body region and a second source/drain region are formed within the pillar. A first gate is coupled to a first side of the pillar for coupling the first and second source/drain regions together when activated. The vertical memory cell also includes a storage capacitor formed on an extended end of the semiconducting pillar and electrically coupled to the second source/drain region.
Claims25
A memory cell, comprising:
- a pillar of semiconductor material extending from a general plane of a substrate, the pillar including a plurality of sides;
- a first source/drain region formed in the substrate and coupled to a bit line implanted in the substrate, wherein the bit line is at least partially offset from the pillar in a direction lateral to the bit line, wherein at least a portion of the bit line extends beyond an outer edge of one side of the pillar, and wherein at least a portion of another side of the pillar extends beyond an edge of the bit line;
- an access transistor including a body region and a second source/drain region both formed within the pillar, the access transistor further including the first source/drain region;
- and
- a first gate on a first side of the pillar and an independent second gate on a second side of the pillar, the first and second gates being differently activated by separate and different activation voltages.
2 more elements
A memory device, comprising:
- an array of memory cells, each memory cell including:
- a pillar of semiconductor material extending from a general plane of a substrate, the pillar including a plurality of sides;
- a first source/drain region formed in the substrate;
- an access transistor including a body region and a second source/drain region formed within the pillar, the access transistor further including the first source/drain region, the access transistor including a first gate on a first side of the pillar and an independent second gate on a second side of the pillar, the first and second gates being differently activated by separate and different activation voltages;
- a plurality of bit lines implanted into the substrate, wherein each of the plurality of bit lines is at least partially offset from the pillar in a direction lateral to the bit line, wherein at least a portion of each of the plurality of bit lines extends beyond an outer edge of one side of the pillar, and wherein at least a portion of another side of the pillar extends beyond an edge of each of the plurality of bit lines, each of the plurality of bit lines in conductive contact with the first source/drain region of the access transistor of at least a plurality of memory cells in a common column of the array;
- and
- a plurality of word lines disposed generally orthogonal to the plurality of bit lines, the plurality of word lines coupled to the first gates of memory cells immediately adjacent to each of the plurality of word lines.
4 more elements
An integrated circuit, comprising:
- a pillar of semiconductor material integral with and extending generally orthogonal from a general plane of a substrate;
- an access transistor including a first source/drain region formed in the substrate and coupled to a bit line implanted in the substrate, wherein the bit line is at least partially offset from the pillar in a direction lateral to the bit line, wherein at least a portion of the bit line extends beyond an outer edge of one side of the pillar, and wherein at least a portion of another side of the pillar extends beyond an edge of the bit line, and a second source/drain region formed on the pillar;
- a first gate on a first side of the pillar and an independent second gate on a second side of the pillar, the first and second gates being differently activated by separate and different activation voltages;
- and
- an interconnection line formed integral to the first source/drain region in the substrate.
2 more elements
A vertical memory cell, comprising:
- a semiconducting pillar extending outwardly from an integrally connected semiconductor substrate;
- a first source/drain region formed in the substrate and coupled to a bit line implanted in the substrate, wherein the bit line is at least partially offset from the pillar in a direction lateral to the bit line, wherein at least a portion of the bit line extends beyond an outer edge of one side of the pillar, and wherein at least a portion of another side of the pillar extends beyond an edge of the bit line;
- a body region and a second source/drain region formed within the pillar;
- a first gate coupled to a first side of the pillar and an independent second gate coupled to a second side of the pillar for electrically coupling together the first and second source/drain regions when activated, the first and second gates being differently activated by separate and different activation voltages;
- and
- a storage capacitor formed on an extended end of the pillar and electrically coupled to the second source/drain region.
3 more elements
A semiconductor substrate on which is fabricated a semiconductor memory, comprising:
- an array of memory cells, each memory cell including:
- a pillar of semiconductor material extending from a general plane of a substrate, the pillar including a plurality of sides;
- a first source/drain region formed in the substrate;
- and
- an access transistor including a body region and a second source/drain region formed within the pillar, the access transistor further including the first source/drain region, the access transistor including at least a first gate on a first side of the pillar and an independent second gate on a second side of the pillar, the first and second gates being differently activated by separate and different activation voltages;
- a plurality of bit lines implanted into the substrate, wherein each of the plurality of bit lines is at least partially offset from the pillar in a direction lateral to the bit line, wherein at least a portion of each of the plurality of bit lines extends beyond an outer edge of one side of the pillar, and wherein at least a portion of another side of the pillar extends beyond an edge of each of the plurality of bit lines, each of the plurality of bit lines in conductive contact with the first source/drain region of the access transistor of at least a plurality of memory cells in a common column of the array;
- and
- a plurality of word lines disposed generally orthogonal to the plurality of bit lines, the plurality of word lines coupled to the first gates of memory cells immediately adjacent to each of the plurality of word lines.
5 more elements
An electronic system comprising an input device, an output device, a memory device, and a processor device coupled to the input, output, and memory devices, at least one of the input, output, memory, and processor devices including a memory cell, comprising:
- a pillar of semiconductor material extending from a general plane of a substrate, the pillar including a plurality of sides;
- a first source/drain region formed in the substrate and coupled to a bit line implanted in the substrate, wherein the bit line is at least partially offset from the pillar in a direction lateral to the bit line, wherein at least a portion of the bit line extends beyond an outer edge of one side of the pillar, and wherein at least a portion of another side of the pillar extends beyond an edge of the bit line;
- an access transistor including a body region and a second source/drain region formed within the pillar, the access transistor further including the first source/drain region;
- and
- a first gate on a first side of the pillar and an independent second gate on a second side of the pillar, the first and second gates being differently activated by separate and different activation voltages.
2 more elements
Dependencies are inferred from the claim text.