Semiconductor device, layout design method thereof, and layout design device using the same

A layout design device for designing a layout of a semiconductor device, comprising:

• input means for inputting device information including placement position information of each unit constituting a semiconductor device which has a multilayer structure provided with a dummy pattern for ensuring flatness, a layout design being carried out separately for each layer constituting the semiconductor device;
• search means for searching, in each layer, a presence of an area which fulfills a configuration condition of a dummy pattern confined area, the configuration condition set in advance, and the searching being based on the device information input by the input means;
• confined area configuration means for setting, in each layer, the dummy pattern confined area, if an area which fulfills the configuration condition is found by the search means, the dummy pattern confined area being set in an area which corresponds to the area found;
• and
• dummy pattern arranging means for arranging a dummy pattern in an area excluding an area in which the dummy pattern confined area is set by the confined area configuration means;
• the configuration condition of the dummy pattern confined area being a condition to include, in top view, at least an area between a pad area and an input-output circuit area, the pad area including a bonding pad formed therein, and the input-output circuit area being adjacent to the pad area and including an input-output circuit formed therein.