Hetero junction bipolar transistor and method of manufacturing the same

#This application claims the benefit of Korean Patent Application No. 10-2005-0120171, filed on Dec. 8, 2005, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

#1. Field of the Invention

#The present invention relates to a hetero-junction bipolar transistor and a method of manufacturing the same, and more particularly, to a hetero-junction bipolar transistor that can increase data processing speed by reducing base resistance and parasitic capacitance and a method of manufacturing the same.

#The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which:

#FIGS. 1 and 2 are cross-sectional views illustrating a method of manufacturing a conventional hetero-junction bipolar transistor; and

#FIGS. 3 through 13 are cross-sectional views illustrating a method of manufacturing a hetero-junction bipolar transistor according to an embodiment of the present invention.

#The present invention will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. The invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like reference numerals refer to like elements throughout the drawings.

#FIGS. 3 through 13 are cross-sectional views illustrating a method of manufacturing a hetero-junction bipolar transistor (HBT) according to an embodiment of the present invention

#Referring to FIG. 3, an n+ InGaAs sub-collector layer 102, a first etch stopper layer 104, an n− InGaAs collector layer 106, a p+ InGaAs base layer 108, a second etch stopper layer 110, an n InP emitter layer 112, an n+ InP emitter grade layer 114, and an n+ InGaAs emitter cap layer 116 are sequentially formed on a semi-insulating InP substrate 100. At this time, the first etch stopper layer 104 may be an InP layer, and the second etch stopper layer 110 may be an InGaAs layer.