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AssigneeTaiwan Semicondutor Manufacturing Co.
InventorsMei-Yun Wang, Cheng-Chen Calvin Hsueh
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A method for fabricating a semiconductor device having a silicided gate that is directed to forming the silicided structures while maintaining gate-dielectric integrity. Initially, a gate structure has, preferably, a poly gate electrode separated from a substrate by a gate dielectric and a metal layer is then deposited over at least the poly gate electrode. The fabrication environment is placed at an elevated temperature. The gate structure may be one of two gate structures included in a dual gate device such as a CMOS device, in which case the respective gates may be formed at different heights (thicknesses) to insure that the silicide forms to the proper phase. The source and drain regions are preferably silicided as well, but in a separate process performed while the gate electrodes are protected by, for example a cap of photoresist or a hardmask structure.
A method of fabricating a semiconductor device, comprising:
A method for fabricating a semiconductor device, comprising:
A method for fabricating a CMOS device having a PFET and an NFET, comprising forming on a semiconductor substrate two gate structures comprising poly gates, forming a source region and a drain region for each of the gates, siliciding each of the source regions and drain regions, etching the PFET poly gate to reduce its thickness, and depositing a metal-containing layer, wherein the metal and the poly gates are at a temperature of greater than about 400° C. such that the metal reacts with substantially all of each of the poly gates to form a silicide.
Dependencies are inferred from the claim text.