Exposure method for upper layer of hole of semiconductor device
AssigneeFujitsu Microelectronics Limited
InventorsFumitoshi Sugimoto, Kiyoshi Ozawa
Life of this patent
Estimating the term…
Abstract
An exposure method executed after processing a hole in a substrate of a semiconductor device, has an exposure step of transferring a pattern on a mask onto an upper layer of the hole and forming a wiring groove by exposure, wherein a quantity of exposure with which a wiring groove 11 just above the hole or the wiring groove in the vicinity of the hole is exposed to light, is greater than a quantity of exposure with which a wiring groove 11A in a position spaced away from just above the hole is exposed to the light.
Claims26
An exposure method applied to a substrate of a semiconductor device including a hole, comprising:
- preparing a mask to cause a quantity of exposure with which a wiring groove just above the hole or a wiring groove in a vicinity and over the hole is exposed to light to be greater than a quantity of exposure with which a wiring groove in a position spaced away from just above the hole is exposed to the light;
- exposing a pattern on the mask to light to transfer the pattern onto an upper layer of the hole and to form the wiring groove.
An exposure method , executed after processing a hole in a substrate of a semiconductor device, comprising:
- exposing a pattern on a mask to light to transfer the pattern onto an upper layer of the hole and to form a wiring groove;
- wherein a quantity of exposure with which the wiring groove just above the hole or the wiring groove in a vicinity and over the hole is exposed to the light is greater than a quantity of exposure with which the wiring groove in a position spaced away from just above the hole is exposed to the light, and
- wherein the exposing the pattern employs a mask having an addition of an auxiliary pattern for adjusting the quantity of exposure to the pattern for exposing the wiring groove to the light.
An exposure method, executed after processing a hole in a substrate of a semiconductor device, comprising:
- exposing a pattern on a mask to light to transfer the pattern onto an upper layer of the hole and to form a wiring groove;
- wherein a quantity of exposure with which the wiring groove just above the hole or the wiring groove in a vicinity and over the hole is exposed to the light is greater than a quantity of exposure with which the wiring groove in a position spaced away from just above the hole is exposed to the light and
- the exposing the pattern includes a dual exposure of exposing one exposure portion to the light twice, and
- wherein the dual exposure employs a first mask having a pattern for exposing the wiring groove to the light and a second mask including an opening having such a dimension that a transferred pattern is not formed on the substrate when exposed to the light in a vicinity of the pattern for exposing the wiring groove of at least an area just above the hole to the light.
An exposure method, executed after processing a hole in a substance of a semiconductor device, comprising:
- exposing a pattern on a mask to light to transfer the pattern onto an upper layer of the hole and to form a wiring groove;
- wherein a quantity of exposure with which the wiring groove just above the hole or the wiring groove in a vicinity and over the hole is exposed to the light is greater than a quantity of exposure with which the wiring groove in a position spaced away from just above the hole is exposed to the light, and
- wherein a quantity of exposure of the wiring groove just above the hole or in the vicinity and over the hole is set corresponding to a hole density of an lower layer of the wiring groove or a vicinal area, and
- a quantity of exposure in an area of which the hole density is higher than a first density, is greater than a quantity of exposure in an area of which the hole density is lower than the first density.
A method of forming a resist pattern, comprising:
- exposing, after a hole has been processed in a substrate of a semiconductor device, a pattern of a wiring groove to light upon a chemical amplification type resist;
- heating the substrate at a temperature of 100°C. through 200°C.;
- and
- further heating a resist area upon which the pattern of the wiring groove is exposed to the light just above the hole or in a vicinity and over the hole.
A method of manufacturing a semiconductor device including a hole, comprising;
- dissolving a solution hindering substance against a chemical amplification type resist after the hole has been processed in a substrate of the semiconductor device with etching gas, by irradiating the substrate with radiation rays;
- and
- coating the chemical amplification type resist after the irradiating of the substrate with the radiation rays.
A method of manufacturing a semiconductor device including a hole, comprising;
- dissolving a solution hindering substance against a chemical amplification type resist after the hole has been processed in a substrate of a semiconductor device with etching gas, by heating the substrate at 100°C. through 200°C. and irradiating the substrate with radiation rays;
- and
- coating the chemical amplification type resist after the heating and the irradiating of the substrate with the radiation rays.
Dependencies are inferred from the claim text.