Semiconductor integrated circuit device
AssigneeRenesas Technology Corp.
InventorsYasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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AssigneeRenesas Technology Corp.
InventorsYasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
Estimating the term…
Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.
A method of manufacturing a semiconductor integrated circuit device, comprising steps of:
A method of manufacturing a semiconductor integrated circuit device, comprising steps of:
Dependencies are inferred from the claim text.