US 7,678,683 B2 · Method of fabricating copper damascene and dual damascene interconnect wiring

Abstract

An integrated circuit and a method of manufacturing the integrated circuit, the method including: (a) providing a substrate; (b) forming a copper diffusion barrier layer on the substrate; (c) forming a dielectric layer on a top surface of the copper diffusion barrier layer; (d) forming a copper damascene or dual damascene wire in the dielectric layer, a top surface of the copper damascene or dual damascene wire coplanar with a top surface of the dielectric layer; (e) forming a first capping layer on the top surface of the wire and the top surface of the dielectric layer; (f) after step (e) performing one or more characterization procedures in relation to said integrated circuit; and (g) after step (e) forming a second capping layer on a top surface of the first capping layer.

Claims33

Dependent claims

A method of manufacturing an integrated circuit, comprising:

(a) providing a substrate;
(b) forming a copper diffusion barrier layer on said substrate;
(c) forming a dielectric layer on a top surface of said copper diffusion barrier layer;
(d) forming a copper damascene or dual damascene wire in said dielectric layer, a top surface of said copper damascene or dual damascene wire coplanar with a top surface of said dielectric layer;
(e) forming a first capping layer on said top surface of said wire and said top surface of said dielectric layer;
after (e), (f) performing one or more characterization procedures in relation to said integrated circuit;
and
after (f), (g) forming a second capping layer on said top surface of said first capping layer.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

11/555,383Filed 1 Nov 2006 · division

Priority

20 Sep 2004

Published

US 2007/0059920 A115 Mar 2007

Granted

16 Mar 2010

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10W 20/075
Of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers: of multilayered…
H10W 20/077
Of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers: on sidewalls or on…
H10W 20/081
Of dielectric parts thereof: by forming openings in the dielectric parts
H10W 20/084
By forming openings in the dielectric parts: for dual-damascene structures

Method of fabricating copper damascene and dual damascene interconnect wiring

Life of this patent

Method of fabricating copper damascene and dual damascene interconnect wiring

Life of this patent

Abstract

Claims33