Vertical device with sidewall spacer, methods of forming sidewall spacers and field effect transistors, and patterning method

A method of manufacturing an integrated circuit, the method comprising:

• providing a semiconductor substrate, wherein the semiconductor substrate comprises a first section including a first material, wherein the first material adjoins a horizontal substrate surface of the semiconductor substrate;
• providing a first structure on the horizontal substrate surface of the semiconductor substrate, the first structure including at least one vertical sidewall adjoining the first section of the substrate surface, wherein the first structure comprises a second section that includes a second material, at least part of the first section is not covered by the first structure, and the second material is exposed at the at least one vertical sidewall;
• and
• providing a sidewall spacer, wherein the sidewall spacer is elongated along the at least one vertical sidewall of the first structure and is formed of a third material resulting from a gaseous precursor, the first and second materials and the gaseous precursor being selected such that the third material is selectively grown on the second material;
• wherein the providing of the first structure comprises:
• providing an inner section of the first structure on the semiconductor substrate, the first structure including at least one vertical sidewall;
• and
• providing a seed liner on the at least one vertical sidewall of the inner section, wherein the seed liner forms the second section.