Deep STI trench and SOI undercut enabling STI oxide stressor
AssigneeFreescale Semiconductor, Inc.
InventorsMichael D. Turner, Suresh Venkatesan, Kurt H. Junker
Life of this patent
Estimating the term…
Abstract
A method for imparting stress to the channel region of a transistor is provided. In accordance with the method, a semiconductor layer (307) is provided which has a dielectric layer (305) disposed beneath it. A trench (319) is created which extends through the semiconductor layer and into the dielectric layer, and the trench is backfilled with a stressor material (320), thereby forming a trench isolation structure. A channel region (326) is defined in the semiconductor layer adjacent to the trench isolation structure.
Claims31
A method for imparting stress to the channel region of a semiconductor device, comprising:
- providing a semiconductor layer disposed on an insulating layer;
- creating a trench which extends through the semiconductor layer and into the insulating layer;
- backfilling the trench with a stressor material;
- and
- creating a channel region adjacent to the backfilled trench;
- wherein the step of backfilling the trench results in the formation of a trench isolation structure.
A method for imparting stress to the channel region of an SOI transistor, comprising:
- providing a semiconductor stack containing a buried oxide layer, an SOI layer, and a hard mask;
- creating a first trench which extends through the hard mask and the SOI layer and which exposes a portion of the oxide layer;
- removing a portion of the oxide layer with an etch that undercuts the SOI layer, thereby forming a second trench;
- and
- backfilling the second trench with a stressor material, thereby forming a trench isolation structure.
A semiconductor device, comprising:
- a semiconductor layer having an insulating layer disposed underneath it;
- a channel region defined in said semiconductor layer;
- and
- a trench isolation structure which is adjacent to said channel region and which extends through said first semiconductor layer and into said insulating layer;
- wherein said trench isolation structure imparts stress to said channel region wherein said trench isolation structure undercuts the semiconductor layer.
A method for imparting stress to the channel region of a semiconductor device, comprising:
- providing a semiconductor layer disposed on an insulating layer;
- creating a trench which extends through the semiconductor layer and into the insulating layer, wherein the trench is formed by (a) using a first etch to create an opening which extends through the semiconductor layer and which exposes a portion of the insulating layer, and (b) using a second etch to remove a portion of the insulating layer;
- backfilling the trench with a stressor material;
- and
- creating a channel region adjacent to the backfilled trench.
A method for imparting stress to the channel region of a semiconductor device, comprising:
- providing a semiconductor layer disposed on an insulating layer;
- creating a trench which extends through the semiconductor layer and into the insulating layer;
- backfilling the trench with a tensile stressor material;
- and
- creating a channel region adjacent to the backfilled trench.
A method for imparting stress to the channel region of a semiconductor device, comprising:
- providing a semiconductor layer disposed on an insulating layer;
- creating a trench which extends through the semiconductor layer and into the insulating layer;
- backfilling the trench with a stressor material;
- and
- creating a channel region adjacent to the backfilled trench;
- wherein the semiconductor layer has a hard mask disposed thereon, wherein the trench extends through the hard mask, and wherein the hard mask comprises a layer of pad oxide having a layer of silicon nitride disposed thereon.
Dependencies are inferred from the claim text.