Memory cell having stressed layers

A method of fabricating a memory cell on a substrate, the method comprising:

• (a) providing a p-doped substrate;
• (b) forming a pair of spaced apart n-doped regions on the substrate to form a source and s drain and define a channel therebetween;
• (c) forming a stack of layers on the channel, the stack of layers comprising, in sequence, (i) a tunnel oxide layer, (ii) a floating gate, (iii) an inter-gate dielectric, and (iv) a control gate;
• (d) forming a polysilicon layer on the source and the drain;
• (e) forming a cover layer covering the stack of layers, the cover layer comprising a spacer layer and a pre-metal-deposition layer;
• (f) forming a plurality of contacts contacting the source, the drain and a silicide layer, the contacts having exposed portions that are exposed through the cover layer;
• and
• (g) forming a shallow isolation trench about n-doped regions, the trench comprising a stressed silicon oxide layer having a tensile stress of at least about 200 MPa, whereby the stressed layer induces a tensile strain in the floating gate that reduces leakage of charge held in the floating gate during operation of the memory cell.