Method of fabricating an enhanced resurf HVPMOS device

A method of fabricating an HV PMOS device, comprising:

• providing a semiconductor substrate having an HV well of a first polarity type, the HV well having a surface and being formed in an epitaxial layer of a second polarity;
• forming one or more pairs of field oxide regions on the substrate, said field oxide regions disposed at least in part over said HV well;
• forming one or more pairs of insulated gates over the HV well between each pair of field oxide regions, the gates having inner edges facing each other and outer edges facing a corresponding one of the field oxide regions;
• masking the substrate to expose predetermined inner portions of the gates and the HV well surface between the gates;
• implanting the exposed portions of the HV well to form buffer and drift regions of the first and second polarity types, respectively, therein that are self-aligned with the inner edges of the gates;
• and
• forming within the drift region a region of gradual dopant concentration profile, said region including a drain region of the second polarity type, said region having a dopant concentration that gradually decreases from a relatively high concentration proximate the drain region to a significantly lower dopant concentration proximate the gates.

A method of fabricating an HV PMOS device, comprising:

• providing a semiconductor substrate having an HV well of a first polarity type, the HV well having a surface and being formed in an epitaxial layer of a second polarity;
• forming one or more pairs of field oxide regions on the substrate, said field oxide regions disposed at least in part over said HV well;
• forming one or more pairs of insulated gates over the HV well between each pair of field oxide regions, the gates having inner edges facing each other and outer edges facing a corresponding one of the field oxide regions;
• forming stacked hetero-doped rims in the HV well and in self-alignment with the outer edges of the gates;
• and
• forming source regions in the stacked hetero-doped rims.

A method of fabricating an HV PMOS device, comprising:

• providing a semiconductor substrate having an HV well of a first polarity type, the HV well having a surface and being formed in an epitaxial layer of a second polarity;
• forming one or more pairs of field oxide regions on the substrate, said field oxide regions disposed at least in part over said HV well;
• forming one or more pairs of insulated gates over the HV well between each pair of field oxide regions, the gates having inner edges facing each other and outer edges facing a corresponding one of the field oxide regions;
• implanting dopants of the first polarity type into the HV well between the field oxide regions and the gates to thereby form source tap regions;
• implanting dopants of the second polarity type into a predetermined portion of the HV well between the gates to thereby form a drain region;
• masking the substrate to expose predetermined inner portions of the gates and the HV well surface between the gates;
• and
• implanting the exposed portions of the HV well to form buffer and drift regions of the first and second polarity types, respectively, therein that are self-aligned with the inner edges of the gates.

A method of fabricating an HV PMOS device, comprising:

• providing a semiconductor substrate having an HV well of a first polarity type, the HV well having a surface and being formed in an epitaxial layer of a second polarity;
• forming one or more pairs of field oxide regions on the substrate, said field oxide regions disposed at least in part over said HV well;
• forming one or more pairs of insulated gates over the HV well between each pair
• of field oxide regions, the gates having inner edges facing each other and outer edges facing a corresponding one of the field oxide regions;
• implanting dopants of the first polarity type into the HV well between the field oxide regions and the gates to thereby form source tap regions;
• forming between each pair of gates a drift region of the second polarity type, said drift region including a drain region of the second polarity type;
• forming a region of gradual dopant concentration profile within the drift region, said region having a dopant concentration that gradually decreases from a relatively high concentration proximate the drain region to a significantly lower dopant concentration proximate the gates;
• forming stacked hetero-doped rims in the HV well and in self-alignment with the outer edges of the gates;
• and
• forming enhanced RESURF regions within the HV well proximate the gates.