Buried bitline with reduced resistance

A method of forming buried bitlines of a flash memory cell array, the method comprising:

• providing a semiconductor substrate comprising a structure of a dielectric layer stack formed on a surface of the semiconductor substrate, a conductive layer formed on the dielectric layer stack, and a cap layer formed on the conductive layer;
• forming trenches into the structure to expose part of the semiconductor substrate;
• implanting dopants into the semiconductor substrate using a tilted implantation process to form pocket regions at opposing edges of the exposed part of the semiconductor substrate, wherein the pocket regions are non-overlapping with each other;
• forming an insulating spacer structure covering sidewalls of the trenches, wherein the insulating spacer structure adjoins to a sidewall of the dielectric layer stack and to part of the semiconductor substrate, and wherein the pocket regions are formed prior to forming the insulating spacer structure;
• after forming the insulating spacer structure, forming a doped semiconductor region within the exposed part of the semiconductor substrate;
• forming a conductive region within the trenches on the doped semiconductor region, the conductive layer partially filling up the trenches;
• and
• filling up the trenches with a dielectric material and removing the cap layer, part of the insulating spacer structure, and part of the dielectric material to expose the conductive layer.