Semiconductor device and manufacturing method thereof
AssigneeRenesas Technology Corp.
InventorKazuyoshi Shiba
Life of this patent
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Abstract
To provide a nonvolatile memory having an excellent data holding property and a technique for manufacturing the memory, a polycrystalline silicon film 7 and an insulating film 8 are sequentially stacked on a gate insulating film 6, then the polycrystalline silicon film 7 and the insulating film 8 are patterned to form gate electrodes 7A, 7B, and then sidewall spacers 12 including a silicon oxide film are formed on sidewalls of the gate electrodes 7A, 7B. After that, a silicon nitride film 19 is deposited on a substrate 1 by a plasma enhanced CVD process so that the gate electrodes 7A, 7B are not directly contacted to the silicon nitride film 19.
Claims15
A method of manufacturing a semiconductor device including a nonvolatile memory cell having a first gate electrode over a first region of a semiconductor substrate and a resistance element over a second region of the semiconductor substrate, comprising:
- (a) forming a first conductive film over the first and second regions,
- (b) forming a first insulating film over the first conductive film,
- (c) patterning the first insulating film and the first conductive film so as to form the first gate electrode over the first region while leaving the first insulating film over the first gate electrode and to form the resistance element over the second region while leaving the first insulating film over the resistance element,
- (d) after step (c), depositing a second insulating film over the semiconductor substrate,
- (e) anisotropically etching the first and second insulating films so as to leave the second insulating film over sidewalls of the first gate electrode and the resistance element while removing the first insulating film,
- (f) performing ion implantation of an impurity into the semiconductor substrate so as to form a first semiconductor region in the first region,
- (g) forming a third insulating film over the semiconductor substrate, after the step (f), and
- (h) patterning the third insulating film so as to leave the third insulating film over the first gate electrode and over the first insulating film while partially exposing an area over the resistance element,
- (i) forming a silicide layer over the first semiconductor region and in the partially exposed area over the resistance element, and
- (j) forming a fourth insulating film over the semiconductor substrate, the fourth insulating film having an etching selectivity ratio different from that of each of the second and third insulating films.
A method of manufacturing a semiconductor device, comprising:
- (a) forming a first conductive film over a first region, a second region, and a third region of a semiconductor substrate,
- (b) patterning the first conductive film so as to leave the first conductive film over the first to third regions,
- (c) after step (b), depositing a first insulating film over the semiconductor substrate,
- (d) anisotropically etching the first insulating film so as to leave the first insulating film over sidewalls of the first conductive film over the first to third regions,
- (e) selectively performing ion implantation of an impurity into the semiconductor substrate so as to form a first semiconductor region in the first region,
- (f) selectively performing ion implantation of an impurity into the semiconductor substrate so as to form a second semiconductor region in the third region,
- (g) after steps (e) and (f), forming a second insulating film over the semiconductor substrate,
- (h) selectively patterning the second insulating film so as to partially expose an area over the first semiconductor region while leaving the second insulating film over the first conductive film and the first insulating film over the first region, partially exposing the first conductive film over the second region, exposing the first conductive film over the third region, and exposing an area over the second semiconductor region,
- (i) forming a silicide layer in the partially exposed area over the first semiconductor region, over the partially exposed first conductive film over the second region, over the exposed first conductive film over the third region, and in the exposed area over the second semiconductor region, and
- (j) after step (i), forming a third insulating film over the semiconductor substrate.
Dependencies are inferred from the claim text.