Subresolution silicon features and methods for forming the same
AssigneeMicron Technology, Inc.
InventorsKevin J. Torek, Mark Fischer, Robert J. Hanson
Life of this patent
Estimating the term…
Abstract
Novel etch techniques are provided for shaping silicon features below the photolithographic resolution limits. FinFET devices are defined by recessing oxide and exposing a silicon protrusion to an isotropic etch, at least in the channel region. In one implementation, the protrusion is contoured by a dry isotropic etch having excellent selectivity, using a downstream microwave plasma etch.
Claims30
A method of forming a FinFET device, the method comprising;
- forming a mesa of semiconductor material on a semiconductor substrate, wherein the mesa surrounded on lateral sides by an isolation material and does not include the isolation material;
- recessing the isolation material to expose lateral sides of the mesa of semiconductor material;
- dry etching the exposed lateral sides of the mesa so as to reduce its width to thereby define a contoured portion of the mesa of semiconductor material;
- and
- forming a gate dielectric to conformally cover the contoured portion of the mesa of the semiconductor material
- forming a gate conductor to conformally cover the gate dielectric covering the contoured portion of the mesa of semiconductor material;
- wherein recessing the isolation material comprises recessing on all lateral sides of the mesa, and dry etching comprises tapering an entire upper portion of the mesa.
The method of claim l, wherein forming the mesa comprises etching trenches in the semiconductor substrate and depositing an isolation material in the trenches.
A method of forming a FinFET device, the method comprising;
- forming a mesa of semiconductor material on a semiconductor substrate, wherein the mesa is surrounded on lateral sides by an isolation material and does not include the isolation material;
- recessing the isolation material to expose lateral sides of the mesa of semiconductor material;
- dry etching the exposed lateral sides of the mesa so as to reduce its width to thereby define a contoured portion of the mesa of semiconductor material;
- forming a gate dielectric to conformally cover the contoured portion of the mesa of the semiconductor material
- forming a gate conductor to conformally cover the gate dielectric covering the contoured portion of the mesa of semiconductor material;
- and
- masking portions of the mesa and isolation material to protect the masked portions from the recessing and dry etching;
- wherein recessing the isolation material comprises selectively etching the isolation material within mask openings corresponding to a pattern for the gate conductor.
A method of defining a lateral dimension for a semiconductor structure, the method comprising;
- forming a semiconductor protrusion extending from a silicon oxide surface;
- isotropically dry etching the semiconductor protrusion to define a contoured portion of the semiconductor protrusion;
- and forming a gate dielectric to conformally cover the contoured portion of the semiconductor protrusion;
- wherein forming the semiconductor protrusion comprises:
- defining a semiconductor mesa surrounded by field isolation regions by shallow trench isolation, wherein the mesa does not include the field isolation regions,
- recessing the field isolation regions surrounding at least portions of the mesa to define the silicon oxide surface, wherein recessing the field isolation regions comprises recessing on all lateral sides of the mesa, and dry etching comprises tapering an entire upper portion of the mesa.
Dependencies are inferred from the claim text.