CMOS fabrication process
AssigneeTexas Instruments Incorporated
InventorsMahalingam Nandakumar, Song Zhao, Amitabh Jain
Life of this patent
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Abstract
Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cm−2 are achieved. Tensile stress in the PMOS from the SMT layer is significantly reduced. The PLDD may also be UHT annealed to reduce end of range dislocations close to the PMOS channel.
Claims16
A method of forming a complementary metal oxide semiconductor (CMOS) integrated circuit (IC), comprising the following steps, performed in the order listed:
- providing a substrate;
- forming an n-channel metal oxide semiconductor (NMOS) gate and a p-channel metal oxide semiconductor (PMOS) gate on said substrate;
- forming p-type lightly doped drain (PLDD) regions in said substrate adjacent to said PMOS gate;
- forming NMOS gate sidewall spacers on lateral surfaces of said NMOS gate and PMOS gate sidewall spacers on lateral surfaces of said PMOS gate;
- ion implanting p-type source and drain (PSD) regions in said substrate adjacent to said PMOS gate sidewall spacers with a first set of p-type dopants and a first carbon species;
- performing a PSD ultra high temperature (UHT) anneal on said PSD regions at a temperature above 1200 C for a time duration between 50 microseconds and 100 milliseconds;
- ion implanting n-type source and drain (NSD) regions in said substrate adjacent to said NMOS gate sidewall spacers with a first set of n-type dopants;
- forming a stress memorization technique (SMT) layer with 500 to 1500 MPa tensile stress on said NMOS gate and said PMOS gate, wherein the instant step is performed after said step of performing a PSD UHT anneal;
- performing a rapid thermal process (RTP) anneal on said CMOS IC at a temperature above 850 C;
- and
- removing said SMT layer.
A method of forming a PMOS transistor, comprising the following steps,
- performed in the order listed:
- providing a substrate;
- forming a PMOS gate on said substrate;
- forming PLDD regions in said substrate adjacent to said PMOS gate;
- forming PMOS gate sidewall spacers on lateral surfaces of said PMOS gate;
- ion implanting PSD regions in said substrate adjacent to said PMOS gate sidewall spacers with a first set of p-type dopants and a first carbon species;
- and
- performing a PSD UHT anneal on said PSD regions at a temperature above 1200 C for a time duration between 50 microseconds and 100 milliseconds.
Dependencies are inferred from the claim text.