Selective formation of stress memorization layer

A method of forming a semiconductor structure, the method comprising:

• providing a semiconductor substrate comprising a first region and a second region;
• forming a first p-type metal-oxide-semiconductor (PMOS) device in the first region, wherein a first gate electrode of the first PMOS device has a first p-type impurity concentration;
• forming a stress memorization layer over the first PMOS device in the first region;
• reducing the stress memorization layer in the first region;
• performing an annealing after the step of reducing the stress memorization layer in the first region;
• removing the stress memorization layer;
• and
• forming a second PMOS device in the second region, wherein a second gate electrode of the second PMOS device has a second p-type impurity concentration, and wherein the first p-type impurity concentration is greater than the second p-type impurity concentration, and wherein the stress memorization layer over the second PMOS device is not reduced when the step of reducing the stress memorization layer in the first region is performed.

A method of forming a semiconductor structure, the method comprising:

• providing a semiconductor substrate comprising a first region and a second region;
• forming a first PMOS device in the first region, wherein a first gate electrode of the first PMOS device has a first p-type impurity concentration;
• forming a second PMOS device in the second region, wherein a second gate electrode of the second PMOS device has a second p-type impurity concentration, and wherein the first p-type impurity concentration is greater than the second p-type impurity concentration;
• forming a stress memorization layer over the first region and the second region;
• reducing the stress memorization layer in the first region;
• performing an annealing after the step of reducing the stress memorization layer;
• and
• removing the stress memorization layer.

A method of forming a semiconductor structure, the method comprising:

• providing a semiconductor substrate comprising a first region and a second region;
• forming a first PMOS device in the first region, wherein a first gate electrode of the first PMOS device has a first p-type impurity concentration;
• forming a second PMOS device in the second region, wherein a second gate electrode of the second PMOS device has a second p-type impurity concentration, and wherein the first p-type impurity concentration is greater than the second p-type impurity concentration;
• forming a stress memorization layer over the first region and the second region;
• reducing the stress memorization layer in the first region;
• performing an annealing after the step of reducing the stress memorization layer;
• and
• removing the stress memorization layer, wherein the step of forming the second PMOS device comprises pre-gate doping a gate electrode of the second PMOS device with a third p-type impurity before patterning a gate dielectric layer for the first PMOS device, wherein the first gate electrode of the first PMOS device has a higher concentration of the third p-type impurity than does the second gate electrode of the second PMOS device.