Local stress engineering for CMOS devices
AssigneeInternational Business Machines Corporation
InventorsQiqing Ouyang, Kathryn T. Schonenberg
Life of this patent
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Abstract
A first dielectric layer is formed over a PFET gate and an NFET gate, and lithographically patterned to expose a PFET area, while covering an NFET area. Exposed PFET active area is etched and refilled with a SiGe alloy, which applies a uniaxial compressive stress to a PFET channel. A second dielectric layer is formed over the PFET gate and the NFET gate, and lithographically patterned to expose the NFET area, while covering the PFET area. Exposed NFET active area is etched and refilled with a silicon-carbon alloy, which applies a uniaxial tensile stress to an NFET channel. Dopants may be introduced into the SiGe and silicon-carbon regions by in-situ doping or by ion implantation.
Claims20
A method of forming a semiconductor structure comprising:
- forming and patterning a first dielectric layer on a semiconductor substrate, wherein a first device region containing a first gate stack is exposed, while a second device region containing a second gate stack is masked by said first dielectric layer;
- forming embedded SiGe regions in said first device region by a first selective epitaxy on both sides of said first gate stack;
- forming and patterning a second dielectric layer on said embedded SiGe regions, wherein an area containing said second gate stack is exposed, while said first device region containing said first gate stack is masked by said second dielectric layer;
- and
- forming embedded silicon-carbon regions in said second device region by a second selective epitaxy on both sides of said second gate stack.
A method of forming a semiconductor structure comprising:
- forming and patterning a first dielectric layer on a semiconductor substrate, wherein a first device region containing a first gate stack is exposed, while a second device region containing a second gate stack is masked by said first dielectric layer;
- forming first source/drain trenches in said first device region by etching silicon from exposed surfaces of said first device region, while said first dielectric layer protects said second device region;
- forming embedded SiGe regions in said first device region by a first selective epitaxy, wherein said embedded SiGe regions are formed in said first source/drain trenches and said embedded SiGe regions comprise Ge from about 15% to about 35% in atomic concentration;
- forming and patterning a second dielectric layer on said embedded SiGe regions, wherein an area containing said second gate stack is exposed, while said first device region containing said first gate stack is masked by said second dielectric layer;
- and
- forming embedded silicon-carbon regions in said second device region by a second selective epitaxy.
A method of forming a semiconductor structure comprising:
- forming and patterning a first dielectric layer on a semiconductor substrate, wherein a first device region containing a first gate stack is exposed, while a second device region containing a second gate stack is masked by said first dielectric layer;
- forming embedded SiGe regions in said first device region by a first selective epitaxy;
- forming and patterning a second dielectric layer on said embedded SiGe regions, wherein an area containing said second gate stack is exposed, while said first device region containing said first gate stack is masked by said second dielectric layer;
- forming second source/drain trenches in said second device region by etching silicon from exposed surfaces of said second device region, while said second dielectric layer protects said first device region;
- and
- forming embedded silicon-carbon regions in said second device region by a second selective epitaxy, wherein said embedded silicon-carbon regions are subsequently formed in said second source/drain trenches and said embedded silicon-carbon regions comprise C from about 0.5% to about 4.0% in atomic concentration.
Dependencies are inferred from the claim text.