Methods of fabricating semiconductor devices including channel layers having improved defect density and surface roughness characteristics

A method of manufacturing a semiconductor device, the method comprising:

• forming an insulating interlayer having an opening extending therethrough on a single crystalline silicon substrate, the opening exposing a surface of the single crystalline silicon substrate;
• forming a single crystalline silicon pattern on the exposed surface of the single crystalline silicon substrate to fill the opening;
• forming a single crystalline silicon layer on the insulating interlayer and the single crystalline silicon pattern, the single crystalline silicon layer having a protrusion extending from a surface thereof;
• forming a sacrificial layer on the single crystalline silicon layer;
• removing a portion of the sacrificial layer and a portion of the protrusion of the single crystalline silicon layer in a first polishing process to define a sacrificial layer pattern and a remaining portion of the protrusion;
• removing the sacrificial layer pattern;
• planarizing the surface of the second single crystalline silicon layer in a second polishing process to remove the remaining portion of the protrusion and define a substantially planar silicon channel layer;
• and
• forming a transistor on the silicon channel layer.

A method for fabricating a semiconductor device, the method comprising:

• forming a single crystalline semiconductor layer on a semiconductor substrate, the single crystalline semiconductor layer having a protrusion extending from a surface thereof;
• forming a sacrificial layer on the single crystalline semiconductor layer;
• performing a first polishing process on the single crystalline semiconductor layer using the sacrificial layer as a polish stop to remove a majority of the protrusion such that the single crystalline semiconductor layer includes a remaining portion of the protrusion and to define a sacrificial layer pattern on the surface of the single crystalline semiconductor layer adjacent the remaining portion of the protrusion;
• removing the sacrificial layer pattern;
• and then
• performing a second polishing process that is different from the first polishing process to remove the remaining portion of the protrusion and define a substantially planar single crystalline semiconductor layer having a substantially uniform thickness.