US 7,678,623 B2Granted

Staggered source/drain and thin-channel TFT structure and fabrication method thereof

AssigneeNational Chiao Tung University

InventorsKow-Ming Chang, Gin-Min Lin

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Abstract

This invention relates to a process for fabricating a staggered source/drain and thin-channel TFT structure, which simplifies the conventional process for fabricating the structure by decreasing the number of mask steps and achieving better results at suppressing the electric field near the drain junction and reducing the leakage current. The process comprises (1) re-crystallizing a-Si into poly-Si (02), which is performed by depositing an a-Si layer on a substrate and then applying a general photolithographic step and a RIE etching step for defining the amorphous Si islands provided with higher regions and lower regions, wherein the residual width of the thin channel of the a-Si is about 5 to 200 nm after etching; then the a-Si is changed into poly-Si (02) after a subsequent annealing; (2) defining the gate region (05), source/drain region (07) and the channel; (3) applying the implantation; and (4) applying the connection.

Claims8

Dependent claims

A method of manufacturing a poly-Si TET structure, wherein the structure comprises a stacked source/drain and a thin channel, wherein the steps comprise:

(1) a step of re-crystallizing a a-Si layer to form a poly-Si layer:
first, deposit an a-Si layer on-top of a substrate, followed by carrying out a general exposure lithography and using etching technique to define a-Si islands with higher regions and lower regions, followed by annealing, in order to re-crystallize the a-Si layer to form a poly-Si layer (02);
(2) a step of defining a gate region, source/drain region and channel region:
respectively stack a gate oxide layer (04) and a poly-Si thin film, followed by carrying out general lithography and using etching to define a gate region (05), source/drain region (07) and channel region;
(3) implementation step:
ionic implantation technique is used to form a heavy doped gate region (05) and source/drain region (07), and ionic activation is carried out;
and
(4) connection step:
deposit a SiO2 protection layer and open a contact window (14), and carry out a connection of a conducting line (10).

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/410,168Filed 24 Apr 2006
Priority: TW 95100731 A9 Jan 2006
Published: US 2007/0161161 A112 Jul 2007
Granted: 16 Mar 2010
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10D 30/6757
Thin-film transistors [TFT]: characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
H10D 30/0314
Characterised by the gate electrodes: of lateral top-gate TFTs comprising only a single gate
H10D 30/0321
Of thin-film transistors [TFT]: comprising silicon, e.g. amorphous silicon or polysilicon
H10D 30/6706
Having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device: for…