Mask for forming landing plug contact hole and plug forming method using the same
AssigneeHynix Semiconductor Inc.
InventorDong Chul Koo
Life of this patent
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Abstract
Disclosed herein are a mask for forming a landing plug contact hole to vertically expose an active region of a semiconductor substrate to a bit line or storage node contact, and a plug forming method using the same. Through the use of the crescent-shaped masks, it is possible to increase the critical dimension at a lower end of the resultant contact hole in contact with an active region of a semiconductor substrate, thereby enabling exposure of a wider area of the active region to be connected with the bit line or storage node contact.
Claims4
A mask for forming landing plug contact holes to vertically expose bar type active regions of a semiconductor substrate to bit line contacts or storage node contacts,
- wherein the mask has plural pairs of landing plug contact patterns arranged, wherein the pattern has a crescent bowed shape having an outwardly shifted and protruded middle portion, and the respective pair of the patterns are positioned to be facing each other so that the respective outwardly shifted and protruded middle portions are directed to the respective outward directions to form an inner space having a cross (+) shape;
- wherein a central part of the inner space having a cross (+) shape formed by the patterns facing each other is a region that a bit line contact is to be formed, and both side parts of the inner space having a cross (+) shape formed by the patterns facing each other are regions that storage node contacts are to be formed;
- and
- wherein the region that a bit line contact is to be formed is opened wider than the regions that storage node contacts are to be formed.
A method of forming landing plugs in an inter-insulation layer comprising:
- forming the inter-insulation layer throughout an upper surface of a semiconductor substrate where certain semiconductor diodes are defined;
- forming contact holes in the inter-insulation layer by means of masks to vertically expose active regions of the semiconductor substrate, wherein the mask has plural pairs of landing plug contact patterns arranged, wherein the pattern has a crescent bowed shape having a outwardly shifted and protruded middle portion, and the respective pair of the patterns are positioned to be faced each other so that the respective outwardly shifted and protruded middle portions are directed to the respective outward directions to form an inner space having a cross (+) shape, wherein a central part of the inner space having a cross (+) shape formed by the patterns facing each other is a region that a bit line contact is to be formed, and both parts of the inner space having a cross (+) shape formed by the patterns facing each other are regions that storage node contacts are to be formed, wherein the region that a bit line contact is to be formed is opened wider than the regions that storage node contacts are to be formed;
- and
- gap-filling a conductive layer in the landing plug contact holes and flattening the conductive layer, thereby forming landing plugs for embedding the contact holes to vertically connect the active regions with the bit lines or storage node contacts.
Dependencies are inferred from the claim text.