# US 7,673,200 B2 · Reprogrammable built-in-self-test integrated circuit and test method for the same

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- Number: US 7,673,200 B2
- Document ID: US7673200B2
- Status: Granted
- Kind: B2
- Application number: 11/870,242
- Filed: 2007-10-10
- Published: 2009-04-16
- Granted: 2010-03-02
- Earliest claimed: 2007-10-10
- Assignees: Asix Electronics Corporation
- Inventors: Hsun-Yao Jan; Ting-Han Su; Cheng-Fang Yang
- Web page: https://patentgrep.com/patent/US7673200B2

## CPC

- G01R 31/31707: {Test strategies (methods for generation of test sequences G01R31/318371)}
- G11C 29/16: using microprogrammed units, e.g. state machines
- G11C 2029/0401: {in embedded memories}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The present invention discloses a reprogrammable built-in-self-test integrated circuit and a test method for the same, wherein test programs are directly stored in the application program memory of the logic chip of a SoC IC, and an external test apparatus is used to load the test programs into the application program memory via a serial transmission interface, and an application CPU is used to read and execute the test programs to perform the bonding-wire connectivity between the logic chip and the memory chip. In the present invention, test vectors can still be flexibly revised after tapeout to increase test coverage. As the test programs are directly stored in the existing application program memory without using additional memory space, and as the test programs are executed by the existing application CPU without using an extra built-in-self-test circuit, the present invention can effectively reduce test cost.

## Claims

### Claim 1

A reprogrammable built-in-self-test integrated circuit comprising:
at least one memory chip for storing data or program; and
a logic chip electrically connected to said at least one memory chip:
the logic chip comprises;
a serial transmission interface providing an electric connection to an external test apparatus;
at least one application program memory storing test programs wherein the test programs being input via said serial transmission interface; and
an application Central Processing Unit (CPU) electrically connected to said at least one memory chip and said application program memory; and
the CPU reading and executing said test programs to perform a test for said memory chip.

### Claim 2 (depends on 1)

The reprogrammable built-in-self-test integrated circuit according to claim 1, wherein said memory chip is a flash memory, a Static Random Access Memory (SRAM), or a Synchronous Dynamic Random Access Memory (SDRAM).

### Claim 3 (depends on 1)

The reprogrammable built-in-self-test integrated circuit according to claim 1, wherein said serial transmission interface supports two modes including:
a test mode, wherein said serial transmission interface receives test programs from said test apparatus and converts said test programs into parallel data and stores said parallel data in said at least one application program memory; and
a normal operation mode, wherein said serial transmission interface functions as a general transmission interface of said application CPU.

### Claim 4 (depends on 1)

The reprogrammable built-in-self-test integrated circuit according to claim 1, wherein said at least one application program memory is a SRAM built into said logic chip and being used to store said test programs or application programs.

### Claim 5 (depends on 4)

The reprogrammable built-in-self-test integrated circuit according to claim 4 wherein,
in a normal operation mode, said application CPU reads and executes said application programs stored in said at least one application program memory; and
in a test mode, said application CPU reads and executes said test programs stored in said at least one application program memory to perform write tests, read tests, comparisons and verifications on said memory chip.

### Claim 6 (depends on 1)

The reprogrammable built-in-self-test integrated circuit according to claim 1, wherein said test apparatus revises said test programs stored in said at least one application program memory via said serial transmission interface.

### Claim 7 (depends on 1)

The reprogrammable built-in-self-test integrated circuit according to claim 1, wherein said test programs are used to test bonding-wire connectivity between said logic chip and said at least one memory chip.

### Claim 8 (depends on 1)

The reprogrammable built-in-self-test integrated circuit according to claim 1, wherein said application CPU outputs results of executing said test programs via pins of said logic chip to said test apparatus for further analysis.

### Claim 9 (depends on 1)

The reprogrammable built-in-self-test integrated circuit according to claim 1, wherein said logic chip and said at least one memory chip are sub-structures of a multi-chip-package (MCP) system-on-chip (SoC) integrated circuit (IC).

### Claim 10 (depends on 1)

The reprogrammable built-in-self-test integrated circuit according to claim 1, wherein said test programs are softwares stored in said test apparatus.

### Claim 11

A method for testing a reprogrammable built-in-self-test integrated circuit comprising:
providing a logic chip and at least one memory chip;
electrically connecting the at least one memory chip to said logic chip;
providing a serial transmission interface, an application program memory, and an application Central Processing Unit (CPU);
providing a test apparatus to reset said integrated circuit to a test mode and to transfer serial data of at least one test programs to a serial transmission interface;
said serial transmission interface converting said serial data of said at least one test programs into parallel data, and storing said parallel data in said application program memory;
said test apparatus resetting said integrated circuit to a normal operation mode;
said application CPU reading and executing said at least one test programs stored in said application program memory;
said at least one test programs generating test vectors to test bonding-wire connectivity between said logic chip and said at least one memory chip; and
generating test data and test results and outputting said test data and said test results to said test apparatus.

### Claim 12 (depends on 11)

The method for testing the reprogrammable built-in-self-test integrated circuit according to claim 11, wherein said outputting said test data and said test results includes said application CPU outputs said test data and said test results via pins of said logic chip to said test apparatus.

### Claim 13 (depends on 11)

The method for testing the reprogrammable built-in-self-test integrated circuit according to claim 11, wherein said serial transmission interface supports said test mode and said normal operation mode;
on said test mode, said serial transmission interface receives test programs from said test apparatus; and
said serial transmission interface converts said test programs into parallel data and stores said parallel data in said application program memory;
on said normal operation mode, said serial transmission interface functions as a general transmission interface of said application CPU.

### Claim 14 (depends on 11)

The method for testing the reprogrammable built-in-self-test integrated circuit according to claim 11, wherein said application program memory is a SRAM built into the logic chip and being used to store said at least one test programs or application programs.

### Claim 15 (depends on 11)

The method for testing the reprogrammable built-in-self-test integrated circuit according to claim 11, wherein after transferring said at least one test programs, said test apparatus revises said at least one test programs having been stored in said application program memory via said serial transmission interface.

### Claim 16 (depends on 11)

The method for testing the reprogrammable built-in-self-test integrated circuit according to claim 11, wherein said logic chip and said at least one memory chip are sub-structures of a multi-chip-package (MCP) system-on-chip (SoC) integrated circuit (IC).

### Claim 17 (depends on 11)

The method for testing the reprogrammable built-in-self-test integrated circuit according to claim 11, wherein said at least one test programs are softwares stored in said test apparatus.