Methods of fabricating multichannel metal oxide semiconductor (MOS) transistors

A method of fabricating a transistor comprising:

• alternately stacking sets of first and second epitaxial layers on an integrated circuit substrate;
• and
• patterning the sets of the first and second epitaxial layers and the integrated circuit substrate to form a trench region on the integrated circuit substrate to define an active region, and a stacked structure including the sets of the first and second epitaxial patterns;
• forming a first insulation pattern on a floor of the trench;
• growing a third epitaxial layer on sidewalls of the sets of first and second epitaxial patterns and sidewalls of the active region higher than the first insulation pattern;
• forming a second insulation pattern on a surface of the integrated circuit substrate, the second insulation pattern defining a gate opening that exposes at least a portion of the third epitaxial layer;
• removing the third epitaxial layer in the gate opening to expose the sets of first and second epitaxial patterns;
• selectively etching the first epitaxial patterns of the sets of first and second epitaxial patterns to form a horizontal channel region having a plurality of spaced apart single crystalline channel layers;
• forming a gate oxide layer on a surface of channel layers;
• forming a gate pattern on the horizontal channel and in gap regions between the channel layers and the gate opening, wherein the gate pattern comprises a plurality of gates formed simultaneously between the plurality of spaced apart single crystalline channel layers and widths of the plurality of gates that contact the plurality of single crystalline channel layers are substantially identical;
• and
• forming a vertical source electrode and a vertical drain electrode on the first insulation pattern penetrating the second insulation pattern to be connected to the third epitaxial layer.

A method of forming a unit cell of a metal oxide semiconductor (MOS) transistor, comprising:

• providing an integrated circuit substrate including a trench and an active region higher than the trench, wherein the active region protrudes from the integrated circuit substrate to function as a horizontal channel;
• forming the horizontal channel between a vertical source region and a vertical drain region, the horizontal channel including at least two single crystalline horizontal channel regions formed in spaced apart patterns, and further including the active region higher than the trench;
• forming a plurality of gates simultaneously between at least two single crystalline horizontal channel regions, wherein widths of the plurality of gates that contact the at least two single crystalline horizontal channel regions are substantially identical;
• forming the vertical source region and the vertical drain region in other patterns at one side of the spaced apart patterns, respectively, wherein the vertical source and drain regions extend along sides of the at least two horizontal channel regions and sides of the active region protruding from the integrated circuit substrate;
• and
• forming a vertical source electrode contacted to a side of the vertical source region and a vertical drain electrode contacted to a side of the vertical drain region.