Generic maximum aposteriori probability decoder for use in software-defined radio systems
AssigneeSamsung Electronics Co., Ltd.
InventorsEran Pisek, Yan Wang, Jasmin Oz
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Abstract
A reconfigurable maximum a-posteriori probability (MAP) calculation circuit that reuses the arithmetic logic unit (ALU) hardware to calculate forward state metrics (alpha values), backward state metrics (beta values), and extrinsic information (lambda values) for the trellis associated with the MAP algorithm. The alpha, beta and lambda calculations may be performed by the same ALU hardware for both binary code (i.e., WCDMA mode) and duo-binary code (i.e, WiBro mode).
Claims21
A reconfigurable maximum a-posteriori probability (MAP) calculation circuit for decoding duo-binary code data and binary code data, the reconfigurable MAP calculation circuit comprising:
- a gamma calculation block for calculating a branch metric value for each branch of a trellis associated the MAP calculation circuit, wherein the gamma calculation block receives:
- in duo-binary mode:
- i) duo-binary inputs (a, b) from a first time interval;
- ii) parity information generated from the duo-binary inputs (a,b);
- and iii) extrinsic information associated with previous nodes in the trellis;
- and
- in binary mode:
- i) a first binary input xi from a first time interval and a second binary input xi+1 from a second time interval;
- ii) first parity information generated from the first binary input xi and second parity information generated from the second binary input xi+1;
- and iii) extrinsic information associated with previous nodes in the trellis;
- and
- a first arithmetic logic unit (ALU) stage for calculating alpha values for each node in the trellis in both duo-binary mode and binary mode, wherein the first ALU stage receives alpha values for previous nodes in the trellis and branch metric data from the gamma calculation block.
A reconfigurable turbo decoder comprising:
- N processing units, each of the N processing units capable of receiving soft input data samples and decoding the received soft input data samples, wherein the N processing units operate independently such that a first one of the N processing units may be selected to decode the received soft input data samples while a second one of the N processing units may be disabled, and wherein each of the N processing units comprises a reconfigurable maximum a-posteriori probability (MAP) calculation circuit for decoding duo-binary code data and binary code data, the reconfigurable MAP calculation circuit comprising:
- a gamma calculation block for calculating a branch metric value for each branch of a trellis associated the MAP calculation circuit, wherein the gamma calculation block receives:
- in duo-binary mode:
- i) duo-binary inputs (a, b) from a first time interval;
- ii) parity information generated from the duo-binary inputs (a,b);
- and iii) extrinsic information associated with previous nodes in the trellis;
- and
- in binary mode:
- i) a first binary input xi from a first time interval and a second binary input xi+1 from a second time interval;
- ii) first parity information generated from the first binary input xi and second parity information generated from the second binary input xi+;
- and iii) extrinsic information associated with previous nodes in the trellis;
- and
- a first arithmetic logic unit (ALU) stage for calculating alpha values for each node in the trellis in both duo-binary mode and binary mode, wherein the first ALU stage receives alpha values for previous nodes in the trellis and branch metric data from the gamma calculation block.
A software-defined radio (SDR) system capable of operating under a plurality of wireless communication standards, the SDR system comprising a reconfigurable maximum a-posteriori probability (MAP) calculation circuit for decoding duo-binary code data and binary code data, the reconfigurable MAP calculation circuit comprising:
- a gamma calculation block for calculating a branch metric value for each branch of a trellis associated the MAP calculation circuit, wherein the gamma calculation block receives:
- in duo-binary mode:
- i) duo-binary inputs (a, b) from a first time interval;
- ii) parity information generated from the duo-binary inputs (a,b);
- and iii) extrinsic information associated with previous nodes in the trellis;
- and
- in binary mode:
- i) a first binary input xi from a first time interval and a second binary input xi+1 from a second time interval;
- ii) first parity information generated from the first binary input xi and second parity information generated from the second binary input xi+1;
- and iii) extrinsic information associated with previous nodes in the trellis;
- and
- a first arithmetic logic unit (ALU) stage for calculating alpha values for each node in the trellis in both duo-binary mode and binary mode, wherein the first ALU stage receives alpha values for previous nodes in the trellis and branch metric data from the gamma calculation block.
Dependencies are inferred from the claim text.