Data processing apparatus and method for performing floating point multiplication

A data processing apparatus for multiplying first and second n-bit significands of first and second floating point operands to produce an n-bit result, the data processing apparatus comprising:

• multiplier means for multiplying the first and second n-bit significands to produce a pair of 2n-bit vectors;
• half adder means for receiving a plurality of most significant bits of the pair of 2n-bit vectors and producing a corresponding plurality of carry and sum bits representing those plurality of most significant bits;
• exponent determination means for determining from the first and second floating point operands a product exponent and determining if that product exponent corresponds to a predetermined exponent value indicative of an underflow range;
• first adder means for performing a first sum operation in order to generate a first result equivalent to the addition of the pair of 2n-bit vectors with an increment value injected at a first predetermined rounding position appropriate for a non-overflow condition, the increment value being either a rounding increment value such that the first result produced is a first rounded result or a logic zero value such that the first result produced is a first unrounded result, the rounding increment value being used unless the exponent determination means has determined that the product exponent corresponds to the predetermined exponent value in which case the logic zero value is used as the increment value, the first adder means being arranged to use as the m most significant bits of the pair of 2n-bit vectors the corresponding m carry and sum bits while the remaining 2n-m least significant bits of the pair of 2n-bit vectors are taken directly from the 2n-bit vectors, the least significant of the m carry bits being replaced with the increment value prior to the first adder means performing the first sum operation;
• second adder means for performing a second sum operation in order to generate a second rounded result equivalent to the addition of the pair of 2n-bit vectors with a rounding increment value injected at a second predetermined rounding position appropriate for an overflow condition, the second adder means being arranged to use as the m−1 most significant bits of the pair of 2n-bit vectors the corresponding m−1 carry and sum bits while the remaining 2n-m+1 least significant bits of the pair of 2n-bit vectors are taken directly from the 2n-bit vectors, the least significant of the m−1 carry bits being replaced with the rounding increment value prior to the second adder means performing the second sum operation;
• and
• selector means for deriving the n-bit result from either the first rounded result, the second rounded result or a predetermined result value, where, if the product exponent corresponds to said predetermined exponent value, the selector means derives the n-bit result from the second rounded result if the first unrounded result has overflowed, and derives the n-bit result from the predetermined result value if the first unrounded result has not overflowed, wherein n and m are integers and 2n is greater than m.

A method of operating a data processing apparatus to multiply first and second n-bit significands of first and second floating point operands to produce an n-bit result, the method comprising the steps of:

• multiplying the first and second n-bit significands to produce a pair of 2n-bit vectors;
• employing half adder logic circuitry to produce from a plurality of most significant bits of the pair of 2n-bit vectors a corresponding plurality of carry and sum bits representing those plurality of most significant bits;
• determining from the first and second floating point operands a product exponent and determining if that product exponent corresponds to a predetermined exponent value indicative of an underflow range;
• performing a first sum operation in order to generate a first result equivalent to the addition of the pair of 2n-bit vectors with an increment value injected at a first predetermined rounding position appropriate for a non-overflow condition, the increment value being either a rounding increment value such that the first result produced is a first rounded result or a logic zero value such that the first result produced is a first unrounded result, the rounding increment value being used unless the product exponent corresponds to the predetermined exponent value in which case the logic zero value is used as the increment value, the first sum operation using as the m most significant bits of the pair of 2n-bit vectors the corresponding m carry and sum bits while the remaining 2n-m least significant bits of the pair of 2n-bit vectors are taken directly from the 2n-bit vectors, the least significant of the m carry bits being replaced with the increment value prior to performing the first sum operation;
• performing a second sum operation in order to generate a second rounded result equivalent to the addition of the pair of 2n-bit vectors with a rounding increment value injected at a second predetermined rounding position appropriate for an overflow condition, the second sum operation using as the m−1 most significant bits of the pair of 2n-bit vectors the corresponding m−1 carry and sum bits while the remaining 2n-m+1 least significant bits of the pair of 2n-bit vectors are taken directly from the 2n-bit vectors, the least significant of the m−1 carry bits being replaced with the rounding increment value prior to performing the second sum operation;
• and
• deriving the n-bit result from either the first rounded result, the second rounded result or a predetermined result value, where, if the product exponent corresponds to said predetermined exponent value, the deriving step derives the n-bit result from the second rounded result if the first unrounded result has overflowed, and derives the n-bit result from the predetermined result value if the first unrounded result has not overflowed, wherein n and m are integers and 2n is greater than m.