Phase adjustment apparatus and method for a memory device signaling system

A method for adjusting phase of data signals, comprising:

• receiving phase vector clock signals, comprising a set of evenly phase shifted clock signals;
• receiving transmit data;
• using a first plurality of the phase vector clock signals, generating a transmit clock having a phase determined in accordance with a digitally stored transmit phase value;
• transmitting the transmit data with a phase determined by the transmit clock;
• using a second plurality of the phase vector clock signals, generating a receive clock having a phase determined in accordance with a digitally stored receiver phase value comprising a receiver phase-select value and a receiver phase-blend value, wherein generating the receive clock comprises
• selecting a pair of said phase vector clock signals in accordance with the receiver phase-select value, and
• interpolating between said pair of phase vector clock signals to generate said receiver clock having a phase between phases of said pair of phase vector clock signals in accordance with the receiver phase-blend value;
• and
• receiving and sampling receive data at times determined by the phase of the receive clock;
• wherein said transmit data and receive data are signals selected from the group consisting of differential pairs of signals and single-ended signals.

A system for data signal phase adjustment, comprising:

• a plurality of data path slices configured to receive a plurality of phase vector clock signals;
• each data path slice comprising:
• a transmit phase adjuster, coupled to an input-output (I/O) interface and configured to receive said phase vector clock signals;
• and
• a receiver phase adjuster coupled to said I/O interface and configured to receive said phase vector clock signals;
• the transmit phase adjuster comprising:
• a transmit clock phase interpolator for adjusting phase of a transmit clock, relative to a pair of the phase vector clock signals, in accordance with a digitally stored transmit phase value, the digitally stored transmit phase value comprising a transmit phase-select value programmed to select the pair of said phase vector clock signals and a transmit phase-blend value programmed to control interpolation of the selected pair of said phase vector clock signals;
• an output circuit configured to time transmission of transmit data in accordance with the transmit clock;
• and
• the receiver phase adjuster comprising:
• a receiver clock phase interpolator for adjusting phase of a receive clock, relative to at least one of the phase vector clock signals, in accordance with a digitally stored receiver phase value;
• and
• an input sampling circuit configured to time receiving of receive data in accordance with the receive clock;
• wherein
• the output circuit includes a transmit data phase adjuster configured to transmit the transmit data with a phase determined by the transmit clock;
• and
• the input sampling circuit includes a receiver data phase adjuster configured to sample the receive data with a phase determined by the receive clock.

A data signal phase adjustment device comprising:

• an input-output (I/O) interface;
• a fine transmit phase adjuster, coupled to said I/O interface and configured to receive a plurality of phase vector clock signals, comprising:
• a transmit clock phase interpolator configured to generate a transmit clock with a phase determined in accordance with a digitally stored transmit phase value, and
• an output circuit configured to time transmission of transmit data in accordance with the transmit clock;
• an intermediate transmit phase adjuster, configured to send data to the fine transmit phase adjuster, for adjusting the phase of the transmit data within a range of phases that is larger than a range of phase adjustment associated with the fine transmit phase adjuster;
• a coarse transmit phase adjuster, configured to send data to the intermediate transmit phase adjuster, for adjusting the phase of the transmit data within a range of phases having a range greater than one cycle of the transmit clock;
• a fine receiver phase adjuster coupled to said I/O interface and configured to receive said plurality of phase vector clock signals, comprising:
• a receiver clock phase interpolator configured to generate a receive clock with a phase determined in accordance with a digitally stored receiver phase value, and
• an input sampling circuit configured to time receiving of receive data in accordance with the receive clock;
• an intermediate receiver phase adjuster, configured to receive data from the fine receiver phase adjuster, for adjusting phase of the receive data within a range of phases that is larger than a range of phase adjustment associated with the fine receiver phase adjuster;
• and
• a coarse receiver phase adjuster, configured to receive data from the intermediate transmit phase adjuster, for adjusting the phase of the receive data within a range of phases having a range greater than one cycle of the receive clock.

A phase adjustment device comprising:

• an input-output (I/O) interface;
• a transmit phase adjuster, coupled to said I/O interface and configured to receive a plurality of phase vector clock signals;
• and
• a receiver phase adjuster coupled to said I/O interface and configured to receive said plurality of phase vector clock signals;
• the transmit phase adjuster comprising:
• a transmit clock phase interpolator configured to generate a transmit clock with a phase determined in accordance with a digitally stored transmit phase value, the digitally stored transmit phase value comprising a transmit phase-select value programmed to select a pair of said phase vector clock signals and a transmit phase-blend value programmed to control interpolation of the selected pair of said phase vector clock signals;
• an output circuit configured to time transmission of transmit data in accordance with the transmit clock;
• and
• the receiver phase adjuster comprising:
• a receiver clock phase interpolator configured to generate a receive clock with a phase determined in accordance with a digitally stored receiver phase value;
• and
• an input sampling circuit configured to time receiving of receive data in accordance with the receive clock;
• wherein the phase vector clock signals comprise a set of evenly phase shifted clock signals, wherein said transmit data and receive data are signals selected from the group consisting of differential pairs of signals and single-ended signals.