Efficient pulse amplitude modulation transmit modulation
AssigneeTexas Instruments Incorporated
InventorsRobert B. Staszewski, Dirk Leipold, Kenneth J. Maggio
Life of this patent
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Abstract
Efficient PAM transmit modulation is provided by a PAM modulator that includes an oscillator (404) that provides a clock signal, CKV, (408). The clock signal 408 and a delayed version (CKV_DLY) 420 of the clock signal are provided to a logic gate (414). The output of logic gate (414) is used as a power amplifier input signal (PA_IN) for radio frequency power amplifier (416). Depending on the relative time delay of the CKV clock signal (408) and the CKV_DLY delayed clock signal (420), the timing and duty cycle of the logic gate (414) duty cycle can be controlled. The duty cycle or pulse-width variation affects the turn-on time of the power amplifier (416); thereby establishing the RF output amplitude.
Claims13
A pulse amplitude modulator, comprising:
- a power amplifier having an input port for receiving an oscillator clock signal and a plurality of digitally controlled parallel connected transistors that provide for amplitude modulation, wherein the plurality of digitally controlled parallel connected transistors comprises a first transistor coupled in parallel with a second transistor;
- a matching network, the matching network coupled to said digitally controlled parallel connected transistors;
- a digitally controlled oscillator (DCO) having an input;
- a tuning word adjustment circuit coupled to the input, the tuning word adjustment circuit being responsive to an amplitude control signal;
- and wherein said DCO is operable to provide the oscillator clock signal;
- and
- a means for amplitude control of an output of the DCO in response to the amplitude control signal.
A pulse amplitude modulator, comprising:
- a power amplifier having an input port for receiving an input signal and a plurality of digitally controlled parallel connected transistors that provide for amplitude modulation, wherein the plurality of digitally controlled parallel connected transistors comprises a first transistor coupled in parallel with a second transistor;
- a matching network, the matching network coupled to said digitally controlled parallel connected transistors;
- a digitally controlled oscillator (DCO) having a second input;
- and
- a tuning word adjustment circuit coupled to the second input, the tuning word adjustment circuit being responsive to an amplitude control signal;
- and wherein said DCO is operable to provide the input signal for the power amplifier.
A transmitter circuit, comprising:
- a pulse amplitude modulator (PAM) including:
- a digitally controlled oscillator (DCO) having an input and further comprising a tuning word adjustment circuit coupled to the input of the DCO, the tuning word adjustment circuit being responsive to an amplitude control signal, the DCO providing a clock signal;
- and a digitally controlled power amplifier receiving and responsive to the DCO clock signal and the amplitude control signal.
Dependencies are inferred from the claim text.