Methods of forming wiring to transistor and related transistor

A method of forming wiring to a transistor, the method comprising:

• forming a transistor on a semiconductor layer positioned over an etch stop layer positioned over a silicon substrate using masks that are mirror images of an intended layout, the forming including forming a gate and a source/drain region for each;
• forming an insulating layer over the transistor;
• bonding the dielectric to another substrate, the another substrate including one of:
• a blank substrate and a substrate including at least one of the following:
• devices and wiring patterned therein;
• removing the silicon substrate to the etch stop layer;
• forming a contact through the etch stop layer to each of the source/drain region and the gate, wherein the contact forming includes:
• patterning and etching a contact via hole through the etch stop layer to each of the source/drain region and the gate,
• etching through the source/drain region to expose a conductor thereof and through or to the gate to expose a conductor thereof, wherein the conductor includes:
• a) for the source/drain region, a silicide of the source/drain region, and b) for the gate:
• b1) in the case that the gate includes polysilicon, a silicide of the gate, or b2) in the case that the gate includes a metal, the metal of the gate, and
• forming metal in the contact via holes;
• and
• forming at least one wiring to the contacts.