Method and apparatus for a zero voltage processor sleep state
AssigneeIntel Corporation
InventorsSanjeev Jahagirdar, George Varghese, John B. Conrad, Robert Milstrey, Stephen A. Fischer, Alon Navch, Shai Rotem
Life of this patent
Estimating the term…
Abstract
Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.
Claims10
A method comprising:
- transitioning to a zero voltage power management state, wherein an operational voltage applied to a processor is reduced to approximately zero volts, the processor includes at least a first core and a second core;
- saving state variables of the processor to a dedicated cache memory that is to remain powered while the operational voltage applied to the processor is reduced to approximately zero, the saving of the state variables of the processor include saving both a state of the first core and a state of the second core when the processor transitions to the zero voltage power management state for synchronizing restoration of the state of the first core and the state of the second core;
- and
- exiting the zero voltage power management state at an operating voltage applied to the processor higher than the approximately zero volts.
An apparatus comprising:
- a processor including at least a first core, a second core, and a dedicated cache memory associated with the processor, the first core having a first unique identifier and the second core having a second unique identifier and the dedicated cache memory to restore the state variables of a particular core based on the unique identifier of that particular core;
- and
- a voltage regulator coupled to the processor to provide an operating voltage to the processor;
- wherein, the voltage regulator is to reduce the operational voltage applied to the processor to approximately zero volts during a transition to a zero voltage power management state for the processor, and after exiting the zero voltage power management state, the voltage regulator is to increase the operating voltage applied to the processor to an operating voltage state by supplying a voltage higher than the approximately zero volts and the operating state of the processor is restored from the dedicated cache memory, and
- wherein the dedicated cache memory is to (i) receive state variables associated with the processor, (ii) restore the state variables of a particular core of the based on the unique identifier of that particular core, and (iii) remain powered while the operational voltage applied to the processor is reduced to approximately zero.
A machine-readable storage medium having stored thereon instructions, which when executed by a machine including a processor, cause the machine to perform the following operations comprising:
- transitioning to a zero voltage power management state, wherein an applied operational voltage is reduced to approximately zero;
- saving state variables to a dedicated cache memory that is to remain powered while the operational voltage is reduced to approximately zero, the state variables include a state variable of a first core of the processor and a state variable of a second core of the processor;
- exiting the zero voltage power management state at a higher operating voltage;
- and
- restoring the state variables from the cache memory after exiting the zero voltage power management state.
Dependencies are inferred from the claim text.