Visual device, interlocking counter, and image sensor

An interlocked counter comprising a synchronous counter comprises, a logic gate for judging end-value, a logic gate for amplifying interlocking signal, at least one latch circuit for interlocking signal, a logic gate for interlocking signal, a logic gate for enable signal, and a logic gate for initialization, wherein

• behavior of said synchronous counter is stopped when a count number arrived at an end value, by that
• said synchronous counter counts a number of pulses of a clock signal when said synchronous counter inputted an enable signal,
• said logic gate for judging end-value generates an interlocking signal when said count number outputted by a synchronous counter coincided with said end value,
• said logic gate for amplifying interlocking signal amplifies said interlocking signal in order to output to an external part, and
• said logic gate for enable signal generates said enable signal when said interlocking signal is not generated,
• said behavior of said synchronous counter is restarted, by that
• each of said latch circuits for interlocking signal memorizes one of said interlocking signals inputted from an external part when said interlocking signal outputted by said logic gate for judging end-value is not generated,
• said logic gate for interlocking signal judges whether all of said latch circuits for interlocking signal memorize said interlocking signals, and
• said logic gate for enable signal generates said enable signal when all of said latch circuits for interlocking signal memorize said interlocking signals, and
• said logic gate for initialization set an initial value to said synchronous counter by using an initialization signal, by that said logic gate for initialization signal inputs said interlocking signal outputted by said logic gate for judging end-value and said enable signal, and generates said initialization signal.