Semiconductor memory device having on-die-termination device and operation method thereof

A semiconductor memory device, comprising:

• an input buffer configured to receive an external termination command to output a termination command;
• a first delay unit configured to delay the termination command by a delay time corresponding to an additive latency to output an additive on-die-termination (ODT) signal using an internal clock as a reference clock;
• a delay control signal generator configured to selectively receive first and second test signals to generate a delay increase signal and a delay decrease signal in response to a fuse option;
• a domain crossing unit configured to adjust a conversion point of the additive ODT signal into a DLL clock domain signal to output a domain crossing signal in response to the delay increase signal and the delay decrease signal;
• a second delay unit configured to delay the domain crossing signal by a delay time corresponding to a column address strobe (CAS) write latency to output a driving control signal using a DLL clock as a reference clock;
• a plurality of termination resistors connected to an output pad in series and parallel;
• and
• a drive controller configured to control the plurality of termination resistors to be connected/disconnected to an output pad in response to the driving control signal.

A method for driving a semiconductor memory device, the method comprising:

• generating a delay control signal to adjust a conversion point into a DLL clock domain;
• generating a driving control signal by delaying a termination driving command by a delay time corresponding to an ODT latency, wherein the driving control signal is converted into the DLL clock domain signal at the conversion point adjusted by the delay control signal;
• and
• switching termination resistors to be connected/disconnected to an output pad in response to the driving control signal.

A method for driving a semiconductor memory device, the method comprising:

• selectively receiving first and second test signals to generate a delay increase signal and a delay decrease signal in response to a fuse option;
• performing a domain crossing to output a domain crossing signal by adjusting a conversion point of an additive ODT signal synchronized with an external clock into a DLL clock domain signal in response to the delay increase signal and the delay decrease signal;
• delaying the domain crossing signal by a delay time corresponding to a column address strobe (CAS) write latency to output a driving control signal using a DLL clock as a reference clock;
• and
• switching termination resistors to be connected/disconnected to an output pad in response to the driving control signal.