# US 7,657,816 B2 · Low-complexity hybrid LDPC code encoder > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,657,816 B2 - Document ID: US7657816B2 - Status: Granted - Kind: B2 - Application number: 11/487,063 - Filed: 2006-07-13 - Published: 2007-02-08 - Granted: 2010-02-02 - Earliest claimed: 2005-07-13 - Assignees: Leanics Corporation - Inventors: Aaron E. Cohen; Keshab K. Parhi - Web page: https://patentgrep.com/patent/US7657816B2 ## CPC - H03M 13/1182: {wherein the structure of the parity-check matrix is obtained by reordering of a random parity-check matrix} - H03M 13/6561: {Parallelized implementations} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract Encoders and methods for designing encoders for Low Density Parity Check (LDPC) and other block codes are presented. An efficient and systematic method for designing partially parallel encoders is presented. A parallelism factor is selected such that the end result for the encoder is similar to the partially parallel G matrix multiplication method. In addition to the method an initial circuit is given for the G matrix multiplication encoder and the RU encoder. A circuit for the hybrid encoder is presented which achieves less power consumption and smaller area than an equivalent encoder based on the G matrix multiplication with a smaller critical path than previous encoders. ## Claims ### Claim 1 A LDPC block code encoder, comprising: a first matrix multiplier coupled to the input information bits and a first memory unit used to generate first set of parity values, a second matrix multiplier coupled to the output of the said first matrix multiplier and the input information bits, a third matrix multiplier coupled to the output of the second matrix multiplier and a second memory unit used to generate the second set of parity values. ### Claim 2 (depends on 1) The block code encoder of claim 1, wherein said encoder is part of a communications transceiver. ### Claim 3 (depends on 1) The LDPC code encoder of claim 1, wherein the LDPC code is a regular code. ### Claim 4 (depends on 1) The LDPC code encoder of claim 1, wherein the LDPC code is an irregular code. ### Claim 5 (depends on 1) The LDPC block code encoder of claim 1, wherein said matrix multipliers are implemented by a plurality of AND gates and EX-OR (exclusive-or) gates. ### Claim 6 (depends on 1) The LDPC block code encoder of claim 1, wherein the said third matrix multiplier is implemented using back substitution. ### Claim 7 (depends on 1) The LDPC block code encoder of claim 1, where the said third matrix multiplier is implemented using a plurality of binary weighted sums, wherein said binary weighted sums are formed by a plurality of AND gates and EX-OR gates. ### Claim 8 (depends on 1) The LDPC block code encoder of claim 1, wherein the said third matrix multiplier is implemented using an elimination method. ### Claim 9 An integrated circuit having a substrate and a low density parity check block code encoder comprising: a first matrix multiplier coupled to the input information bits and a first memory unit used to generate first set of parity values, a second matrix multiplier coupled to the output of the first matrix multiplier and the input information bits, a third matrix multiplier coupled to the output of the second matrix multiplier and a second memory unit used to generate the second set of parity values. ### Claim 10 (depends on 9) The integrated circuit of claim 9, wherein the said LDPC block code encoder is part of a communications transceiver. ### Claim 11 (depends on 9) The integrated circuit of claim 9 comprising the block code encoder, wherein the said LDPC code is a regular code. ### Claim 12 (depends on 9) The integrated circuit of claim 9 comprising the LDPC block code encoder, wherein the said LDPC code is an irregular code. ### Claim 13 (depends on 9) The integrated circuit of claim 9 comprising the LDPC block code encoder, wherein the said matrix multipliers are implemented by a plurality of AND gates and EX-OR (exclusive-or) gates. ### Claim 14 (depends on 9) The integrated circuit of claim 9 comprising the LDPC block code encoder, wherein the said third matrix multiplier is implemented using back substitution. ### Claim 15 (depends on 9) The integrated circuit claim 9 comprising the LDPC block code encoder, wherein the said third matrix multiplier is implemented using a plurality of binary weighted sums, wherein said binary weighted sums are formed by a plurality of AND gates and EX-OR gates. ### Claim 16 (depends on 9) The integrated circuit of claim 9 comprising the LDPC block code encoder, wherein the said third matrix multiplier is implemented using an elimination method. ### Claim 17 A method to implement a LDPC block code encoder, comprising the steps: a) converting the H matrix to an upper triangular form, b) computing the first set of parity values by a first matrix multiplication, c) Computing an intermediate result by a second matrix multiplication, d) computing the second set of parity values by using the result of the matrix multiplication in part (c), wherein this step is implemented comprising the sub-steps: (i) selecting a method to implement this computation based on either matrix multiplication or back substitution or other elimination methods, (ii) selecting a level of parallelism if needed, and (iii) applying look-ahead to the method in (i) using the level of parallelism in step (ii) if needed.