Low-voltage operational amplifier and operational amplifying method

A low voltage operational amplifier, comprising:

• a differential amplifying stage configured to amplify a difference between a first signal and a second signal that constitute a differential pair using an input pair of NMOS transistors, and configured to output an amplified first signal and an amplified second signal;
• an output amplifying stage configured to amplify a difference between the amplified first signal and the amplified second signal using an input pair of PMOS transistors, and configured to output a first output signal and a second output signal that constitute a differential pair;
• and
• a compensation stage configured to receive the amplified first signal, the amplified second signal, the first output signal, and the second output signal, and configured to reduce a settling time of the first output signal and the second output signal,
• wherein the compensation stage includes:
• a first transistor having a gate that receives a first bias signal, and a source that is connected to a power supply voltage,
• a second transistor having a gate that receives the first bias signal, and a source that is connected to the power supply voltage,
• a third transistor having a gate that receives a second bias signal, and a source that is connected to a drain of the first transistor,
• a fourth transistor having a gate that receives the second bias signal, and a source that is connected to a drain of the second transistor,
• a fifth transistor having a gate that receives a common mode feedback signal, a drain that is connected to a drain of the third transistor, and a source that is connected to a ground voltage,
• a sixth transistor having a gate that receives the common mode feedback signal, a drain that is connected to a drain of the fourth transistor, and a source that is connected to the ground voltage,
• a first compensation capacitor having a terminal that is connected to the drain of the first transistor, and another terminal that receives the second output signal, and
• a second compensation capacitor having a terminal that is connected to the drain of the second transistor, and another terminal that receives the first output signal, and
• wherein:
• the amplified first signal is applied to the drain of the fourth transistor and the drain of the sixth transistor, and
• the amplified second signal is applied to the drain of the third transistor and the drain of the fifth transistor.