US 7,636,408 B2 · Reliable startup and steady-state of estimation based CDR and DFE

Abstract

An apparatus and methods for recovering a clock and a data stream from a source synchronous input data stream are disclosed. The apparatus comprises a filter, a decision feedback equalizer (DFE), a phase error detector, and a clock generator. The input data stream is coupled to the filter and the DFE. The DFE synchronizes the input data stream to a clock generated by the clock generator. A filter output and a DFE output are each coupled to the phase error detector. During an initialization period, the phase error detector conveys a phase error to the clock generator based on one or more phase error estimates of the filter output and during a period of steady-state operation, the phase error detector conveys a phase error to the clock generator based on one or more phase error estimates of the DFE output. The output of the DFE comprises a recovered data stream.

Claims20

Dependent claims

An apparatus configured to recover a clock and data from an input data stream, the apparatus comprising:

a filter;
a decision feedback equalizer (DFE);
and
a phase error detector;
wherein the input data stream is coupled to the filter and the decision feedback equalizer (DFE);
wherein the DFE is configured to synchronize the input data stream to a clock;
wherein an output of the filter and an output of the DFE are each coupled to the phase error detector;
and
wherein the phase error detector is configured to convey a phase error based on one or more phase error estimates of the output of the filter and/or the output of the DFE.

6 more elements

Dependencies are inferred from the claim text.

Reliable startup and steady-state of estimation based CDR and DFE

Life of this patent

Reliable startup and steady-state of estimation based CDR and DFE

Life of this patent

Abstract

Claims20