Execution of parallel groups of threads with per-instruction serialization
AssigneeNVIDIA Corporation
InventorsJohn Erik Lindholm, Stuart F. Oberman
Life of this patent
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Abstract
In a processor, a SIMD group (a group of threads for which instructions are issued in parallel using single instruction, multiple data instruction issue techniques) is logically divided into two or more “SIMD subsets,” each containing one or more of the threads in the SIMD group. Each SIMD subset is associated with a different instance of a variable state parameter. The processor determines which of the instructions to be executed for the SIMD group rely on the state variable and serializes execution of such instructions so that the instruction is executed separately for each SIMD subset. Instructions that do not rely on the state variable are advantageously not serialized.
Claims16
A method for processing data in a parallel processor, the method comprising:
- defining a single-instruction, multiple-data (SIMD) group comprising a plurality of threads to execute a same program in parallel, wherein the SIMD group includes a first subset of threads associated with a first instance of a state variable and a second subset of threads associated with a second instance of the state variable;
- launching the SIMD group on a same clock cycle so that the SIMD group begins in a synchronized state;
- receiving a series of instructions of the program to be executed for each thread of the SIMD group;
- and
- for each instruction of the series that is received:
- determining whether the state variable affects execution of the instruction;
- in the event that the state variable does not affect execution of the instruction, executing the instruction in parallel for all of the threads of the SIMD group;
- and
- in the event that the state variable affects execution of the instruction:
- executing the instruction in parallel for all of the threads of the first subset using the first instance of the state variable;
- and
- executing the instruction in parallel for all of the threads of the second subset using the second instance of the state variable,
- wherein execution of the instruction for the threads of the second subset is serial relative to execution of the instruction for the threads of the first subset.
A processor comprising:
- a plurality of processing engines configured to execute a SIMD group comprising a plurality of threads to execute a same program in parallel, each one of the processing engines being associated with a different one of the plurality of threads, wherein the SIMD group includes a first subset of threads associated with a first instance of a state variable and a second subset of threads associated with a second instance of a state variable;
- and
- a core interface coupled to issue logic the core interface configured to launch the SIMD group on a same clock cycle so that the SIMD group begins in a synchronized state;
- the issue logic coupled to the plurality of processing engines, the issue logic configured to issue one instruction in parallel to the processing engines, wherein each processing engine executes the instruction for the associated one of the plurality of threads of the SIMD group,
- the issue logic including a scheduler configured to determine whether the state variable affects execution of the instruction to be issued,
- wherein the scheduler is further configured to schedule the instruction for parallel execution by all of the processing engines in the event that the state variable does not affect execution of the instruction and, in the event that the state variable does affect execution, to schedule the instruction for parallel execution by the processing engines associated with threads in the first subset of threads and for parallel execution by the processing engines associated with threads in the second subset of threads, wherein execution of the instruction for the threads in the second subset is serial relative to execution of the instruction for the threads in the first subset.
Dependencies are inferred from the claim text.