Semiconductor package including a top-surface metal layer for implementing circuit features

A semiconductor package, comprising:

• a substrate;
• a semiconductor die mounted to the substrate, wherein the semiconductor die is electrically connected to a circuit pattern of the substrate, the substrate having a plurality of bottom side electrical terminals on a bottom side for providing electrical connection to the semiconductor die;
• an encapsulation encapsulating the semiconductor die and at least a top surface of the substrate;
• via holes laser-ablating through the encapsulation;
• electrically conductive vias formed by depositing conductive material within the via holes;
• channels laser-ablated in a top surface of the encapsulation;
• and
• at least one electrical feature within the channels and in direct contact with the encapsulation, wherein the at least one electrical feature is electrically connected to the circuit pattern of the substrate by at least one of the vias.

A method of manufacturing a semiconductor package, comprising:

• mounting a semiconductor die to a substrate;
• electrically connecting the semiconductor die to a circuit pattern of the substrate, wherein the substrate has a plurality of bottom side electrical terminals on a bottom side for providing electrical connection to the semiconductor die;
• encapsulating the semiconductor die and at least the top surface of the substrate to form an encapsulation;
• laser-ablating via holes through the encapsulation;
• depositing conductive material within the via holes to form vias;
• and
• forming a metal layer in direct contact with the encapsulation and disposed at a top surface of the encapsulation that implements at least one electrical feature of the semiconductor package on the top surface of the encapsulation, wherein the at least one electrical feature is electrically connected to the circuit pattern of the substrate by at least one of the vias.