Method of and apparatus for reducing settling time of a switched capacitor amplifier

A circuit comprising:

• a first sampling capacitor having a first bottom plate and a first top plate and a second sampling capacitor having a second bottom plate and a second top plate;
• first and second circuit input nodes for receiving first and second differential signals, respectively;
• a first sampling switch coupled between the first circuit input node and the first top plate and configured to selectively apply the first differential signal to the first top plate and a second sampling switch coupled between the second circuit input node and the second top plate configured to selectively apply the second differential signal to the second top plate;
• a differential amplifier including first and second amplifier input nodes and first and second amplifier output nodes configured to receive and differentially amplify first and second input signals applied to the first and second amplifier input nodes, respectively, to produce first and second differential output signals at the first and second amplifier output nodes, respectively;
• a first decoupling switch coupled between the first bottom plate and the first amplifier input node and a second decoupling switch coupled between the second bottom plate and the second amplifier input node;
• a common mode voltage line;
• first and second bottom plate switches, configured to selectively connect the common mode voltage line to the first bottom plate and the second bottom plate whereby, when the first signal and the second signal are applied to the respective first and second top plates and the common mode voltage is applied to the respective first and second bottom plates, the first and second sampling capacitors sample the respective first and second signals;
• and
• a first reset switch coupled between the common mode voltage line and the first amplifier input node and a second reset switch coupled between the common mode voltage line and the second amplifier input node, whereby the first and second reset switches are configured to apply the common mode voltage to the first and second amplifier input nodes when the first and second sampling capacitors sample the respective first and second signals.

A method of operating a switched capacitor differential amplifier circuit, comprising:

• disconnecting a first end of a first sampling capacitor from a first input node of an amplifier and disconnecting a first end of a second sampling capacitor from a second input node of the amplifier;
• connecting the first ends of the first and second capacitors to a reference voltage;
• when the first ends of the first and second capacitors are disconnected from the respective first and input nodes of the amplifier, coupling the respective second ends of the first and second capacitors to receive a first input signal and a second input signal, respectively;
• and
• while the first and second input signals are connected to the first and second sampling capacitors, respectively, applying the reference voltage to the first and second input nodes of the differential amplifier and disconnecting the reference voltage from the first and second input nodes of the differential amplifier by opening a reset switch, wherein the reset switch is configured to cancel charge injected into the first and second input nodes of the differential amplifier when the reset switch is opened.

A pipelined analog to digital converter comprising:

• a plurality of cascade connected analog to digital converting stages, each stage configured to convert a portion of an analog signal into at least one digital bit,
• each stage comprising at least one switched capacitor amplifier, the at least one switched capacitor amplifier comprising:
• at least one sampling capacitor, configured to sample an input signal during a sampling phase;
• an differential amplifier configured to receive the input signal from the at least one sampling capacitor via at least one differential amplifier input node;
• at least one decoupling switch configured to isolate the at least one sampling capacitor from the amplifier during the sampling phase and to connect the at least one sampling capacitor to the amplifier during an amplifying phase;
• and
• at least one reset switch configured to connect the at least one differential amplifier input node to a reference voltage during the sampling phase to reset the at least one differential amplifier input node wherein the reset switch is configured to cancel charge injected into the differential input when the reset switch is opened.