# US 7,630,875 B2 · Automatic time warp for electronic system simulation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,630,875 B2 - Document ID: US7630875B2 - Status: Granted - Kind: B2 - Application number: 11/160,430 - Filed: 2005-06-23 - Published: 2007-01-11 - Granted: 2009-12-08 - Earliest claimed: 2005-06-23 - Assignees: CPU Technology, Inc. - Inventors: Edward C. King; Alan G. Smith; Jeffrey S. Hammond; Richard S. Czyzewski - Web page: https://patentgrep.com/patent/US7630875B2 ## CPC - G06F 30/33: Design verification, e.g. functional simulation or model checking - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A simulation of an electronics system which performs a set of operations of interest. A simulated supervisory circuit detects a state in which all the operations have been completed, and also determines the amount of time until the occurrence of the next relevant event. Simulation time is then advanced by that amount of time. This enables simulation time corresponding to an inactive system to be eliminated. ## Claims ### Claim 1 A computer-implemented method for efficiently simulating an electronic system, comprising: using a computer to perform steps including: determining a state of said simulated electronic system; determining the occurrence of a next relevant system event in said simulated electronic system when said simulated electronic system state is determined to be idle; advancing a simulation time to immediately prior to said occurrence of said next relevant system event; calculating a state of said simulated electronic system at said advanced simulation time so that said state of said simulated electronic system is advanced; and further advancing said simulated electronic system by single simulated clock periods until a predetermined wait time has elapsed regardless of whether the simulated electronic system state is idle whereby actual time for simulating said electronic system by said computer is reduced. ### Claim 2 (depends on 1) The method of claim 1 further comprising repeating said determining, next relevant system event determining, simulation time advancing, and electronic system state calculating steps. ### Claim 3 (depends on 1) The method of claim 1 wherein said determining step comprises inspecting a predefinable subset of said simulated electronic system. ### Claim 4 (depends on 1) The method of claim 1 further comprising determining next relevant events in said electronic system. ### Claim 5 (depends on 1) The method of claim 1 wherein said further advancing said simulated electronic system by single simulated clock periods step comprises advancing said simulation time of said simulated electronic system by a simulation clock period and calculating said electronic system state at said advanced single simulated clock period. ### Claim 6 (depends on 1) The method of claim 1 wherein said advancing said simulation time step comprises advancing said simulation time by a simulation clock period and calculating said electronic system state at said advanced simulation time when said simulated electronic system is not in an idle state. ### Claim 7 (depends on 1) The method of claim 1 wherein said advancing step comprises advancing a simulation clock and calculating said electronic system state at said advanced simulation clock time when said simulated electronic system is not in an idle state. ### Claim 8 (depends on 1) The method of claim 1 wherein said next relevant system event determining step comprises determining the occurrence of each event on an events list. ### Claim 9 A computer readable storage medium on which are recorded executable computer code which when executed cause a processor to perform the steps comprising: determining a state of a simulated electronic system; determining the occurrence of a next relevant system event in said simulated electronic system when said simulated electronic system is determined to be idle; advancing a simulation time immediately prior to said occurrence of said next relevant system event; calculating a state of said simulated electronic system at said advanced simulation time so that said state of said simulated electronic system is advanced whereby actual time for simulating said electronic system is reduced; and further advancing said simulated electronic system by single simulated clock periods until a predetermined wait time has elapsed regardless of whether the simulated electronic system state is idle; whereby actual time for simulating said electronic system is reduced. ### Claim 10 (depends on 9) The computer readable storage medium of claim 9 further comprising repeating said determining, next relevant system event determining, simulation time advancing, and electronic system state calculating code operations. ### Claim 11 (depends on 9) The computer readable storage medium of claim 9 wherein said determining step comprises inspecting a predefinable subset of said simulated electronic system. ### Claim 12 (depends on 9) The computer readable storage medium of claim 9 further comprising determining next relevant events in said electronic system. ### Claim 13 (depends on 9) The computer readable storage medium of claim 9 wherein said further advancing said simulated electronic system by single simulated clock period steps comprises advancing said simulation time of said simulated electronic system by a simulation clock period and calculating said electronic system state at said advanced single simulated clock period. ### Claim 14 (depends on 9) The computer readable storage medium of claim 9 wherein said advancing simulation time step comprises advancing said simulation time by a simulation clock period and calculating said electronic system state at said advanced simulation time when said simulated electronic system is not in an idle state. ### Claim 15 (depends on 9) The computer readable storage medium of claim 9 wherein said advancing simulation time step comprises advancing a simulation clock and calculating said electronic system state at said advanced simulation clock time when said simulated electronic system is not in an idle state. ### Claim 16 (depends on 9) The computer readable storage medium of claim 9 wherein said next relevant system event determining step comprises determining the occurrence of each event on an events list.