# US 7,629,616 B2 · Silicon carbide self-aligned epitaxial MOSFET for high powered device applications

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- Number: US 7,629,616 B2
- Document ID: US7629616B2
- Status: Granted
- Kind: B2
- Application number: 11/711,703
- Filed: 2007-02-28
- Published: 2008-08-28
- Granted: 2009-12-08
- Earliest claimed: 2007-02-28
- Assignees: Cree, Inc.
- Inventors: Christopher Harris; Kent Bertilsson; Andrei Konstantinov
- Web page: https://patentgrep.com/patent/US7629616B2

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 12/031: {of IGBTs}
- H10D 30/0295: {using recessing of the source electrodes}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 62/8325: {Silicon carbide}
- H10D 64/2527: {for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/516: {the thicknesses being non-uniform}
- Y10S 438/903: Catalyst aided deposition
- Y10S 438/969: Simultaneous formation of monocrystalline and polycrystalline regions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- Y10S: TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

## Abstract

A self-aligned, silicon carbide power metal oxide semiconductor field effect transistor includes a trench formed in a first layer, with a base region and then a source region epitaxially regrown within the trench. A window is formed through the source region and into the base region within a middle area of the trench. A source contact is formed within the window in contact with a base and source regions. The gate oxide layer is formed on the source and base regions at a peripheral area of the trench and on a surface of the first layer. A gate electrode is formed on the gate oxide layer above the base region at the peripheral area of the trench, and a drain electrode is formed over a second surface of the first layer.

## Claims

### Claim 1

A MOSFET comprising:
a first layer having opposite first and second surfaces, and a trench extending from the first surface into the first layer, the first layer having a first conductivity type;
a first epitaxial layer within the trench on sidewalls and a bottom of the trench, the first epitaxial layer having a second conductivity type opposite the first conductivity type;
a second epitaxial layer within the trench on the first epitaxial layer, the second epitaxial layer having the first conductivity type;
at least two oxide spacers on the second epitaxial layer;
a source contact between the oxide spacers and in contact with the first and second epitaxial layers;
a gate oxide layer on the first surface of the first layer, and on a surface of the first epitaxial layer that is over the trench that is not between the oxide spacers;
a gate electrode on the gate oxide layer over the surface of the first epitaxial layer; and
a drain electrode over the second surface of the first layer.

### Claim 2 (depends on 1)

The MOSFET of claim 1, further comprising an impurity region in the bottom of the trench, the impurity region having the second conductivity type and a dopant concentration greater than a dopant concentration of the first epitaxial layer.

### Claim 3 (depends on 1)

The MOSFET of claim 1, wherein the first epitaxial layer has a non-uniform dopant profile with a dopant concentration lowest near the surface of the first epitaxial layer.

### Claim 4 (depends on 1)

The MOSFET of claim 1, wherein the first layer has a dopant profile graded in a vertical direction from the first surface to the second surface, with a dopant concentration lowest near a bottom of the trench and greater near the first and second surfaces.

### Claim 5 (depends on 1)

The MOSFET of claim 1, wherein the first layer and the first and second epitaxial layers are silicon carbide.

### Claim 6 (depends on 1)

The MOSFET of claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.

### Claim 7

A device comprising:
a first layer having opposite first and second surfaces, and a trench extending from the first surface toward the second surface, the first layer having a first conductivity type;
a first epitaxial layer within the trench on sidewalls and a bottom of the trench, the first epitaxial layer having a second conductivity type opposite the first conductivity type;
a second epitaxial layer within the trench on the first epitaxial layer, the second epitaxial layer having the first conductivity type;
at least two oxide spacers on the second epitaxial layer;
a source contact between the oxide spacers and in contact with the first and second epitaxial layers;
a gate oxide layer on the first surface of the first layer, and on a surface of the first epitaxial layer;
a gate electrode on the gate oxide layer over the surface of the first epitaxial layer; and
a drain electrode over the second surface of the first layer.

### Claim 8 (depends on 7)

The device of claim 7, further comprising an impurity region in the bottom of the trench, the impurity region having the second conductivity type and a dopant concentration greater than a dopant concentration of the first epitaxial layer.

### Claim 9 (depends on 7)

The device of claim 7, wherein the first epitaxial layer has a non-uniform dopant profile with a dopant concentration lowest near the surface of the first epitaxial layer.

### Claim 10 (depends on 7)

The device of claim 7, wherein the first layer has a dopant profile graded in a vertical direction from the first surface to the second surface, with a dopant concentration lowest near a bottom of the trench and greater near the first and second surfaces.

### Claim 11 (depends on 7)

The device of claim 7, wherein the first layer and the first and second epitaxial layers are silicon carbide.

### Claim 12 (depends on 7)

The device of claim 7, wherein the first conductivity type is n-type and the second conductivity type is p-type.

### Claim 13

A MOSFET comprising:
a first layer having opposite first and second surfaces, and a trench extending from the first surface into the first layer, the first layer having a first conductivity type;
a first epitaxial layer within the trench on sidewalls and a bottom of the trench, the first epitaxial layer having a second conductivity type opposite the first conductivity type;
a second epitaxial layer within the trench on the first epitaxial layer, the second epitaxial layer having the first conductivity type;
oxide spacers over the trench on the second epitaxial layer;
a source contact within the trench between and in direct contact with the oxide spacers, and also in contact with the first and second epitaxial layers;
a gate oxide layer on the first surface of the first layer, and on a surface of the first epitaxial layer;
a gate electrode on the gate oxide layer over the surface of the first epitaxial layer; and
a drain electrode over the second surface of the first layer.

### Claim 14 (depends on 13)

The MOSFET of claim 13, further comprising an impurity region in the bottom of the trench, the impurity region having the second conductivity type and a dopant concentration greater than a dopant concentration of the first epitaxial layer.

### Claim 15 (depends on 13)

The MOSFET of claim 13, wherein the first epitaxial layer has a non-uniform dopant profile with a dopant concentration lowest near the surface of the first epitaxial layer.

### Claim 16 (depends on 13)

The MOSFET of claim 13, wherein the first layer has a dopant profile graded in a vertical direction from the first surface to the second surface, with a dopant concentration lowest near a bottom of the trench and greater near the first and second surfaces.

### Claim 17 (depends on 13)

The MOSFET of claim 13, wherein the first layer and the first and second epitaxial layers are silicon carbide.

### Claim 18 (depends on 13)

The MOSFET of claim 13, wherein the first conductivity type is n-type and the second conductivity type is p-type.

### Claim 19

A MOSFET comprising:
a first layer having opposite first and second surfaces, and a trench extending from the first surface into the first layer, the first layer having a first conductivity type;
an epitaxial base layer within the trench on sidewalls and a bottom of the trench, the epitaxial base layer having a second conductivity type opposite the first conductivity type;
an epitaxial source layer within the trench on the epitaxial base layer and extending out of and over the trench, the epitaxial source layer having the first conductivity type;
oxide spacers on the epitaxial source layer and extending out of and over the trench;
a source contact within the trench between the oxide spacers and in contact with the epitaxial base and source layers;
a gate oxide layer on the first surface of the first layer, and on a surface of the epitaxial base layer;
a gate electrode on the gate oxide layer over the surface of the epitaxial base layer; and
a drain electrode over the second surface of the first layer.

### Claim 20 (depends on 19)

The MOSFET of claim 19, further comprising an impurity region in the bottom of the trench, the impurity region having the second conductivity type and a dopant concentration greater than a dopant concentration of the epitaxial base layer.

### Claim 21 (depends on 19)

The MOSFET of claim 19, wherein the epitaxial base layer has a non-uniform dopant profile with a dopant concentration lowest near the surface of the epitaxial base layer.

### Claim 22 (depends on 19)

The MOSFET of claim 19, wherein the first layer has a dopant profile graded in a vertical direction from the first surface to the second surface, with a dopant concentration lowest near a bottom of the trench and greater near the first and second surfaces.

### Claim 23 (depends on 19)

The MOSFET of claim 19, wherein the first layer and the epitaxial base and source layers are silicon carbide.

### Claim 24 (depends on 19)

The MOSFET of claim 19, wherein the first conductivity type is n-type and the second conductivity type is p-type.