Bit stream compatible FPGA to MPGA conversions

A computer implemented bit-stream based design conversion method, comprising:

• providing a field programmable gate array (FPGA) device that is convertible into a mask programmable gate array (MPGA) device, wherein:
• a layout of transistors on a silicon substrate is identical between the two devices;
• and
• a plurality of metal layouts to interconnect said transistors are identical between the two devices;
• and
• receiving a random access memory (RAM) bit-stream for a user to program a portion of logic in said FPGA;
• and
• providing at least one custom metal pattern to identically program the same portion of logic in the MPGA, wherein said bit-stream data is used to generate said at least one custom metal pattern,
• wherein each of said FPGA and MPGA devices comprises an exact layout of a portion of interconnect wires to couple one or more of said logic blocks;
• and
• in said bit stream to configure the FPGA, a second portion of bits determine the interconnect wire coupling of said one or more logic blocks in the FPGA;
• and
• said conductive pattern to configure the MPGA, wherein the result of said second portion of bits in the FPGA is replicated in the second portion of the conductive pattern to provide identical interconnect wire coupling of said one or more logic blocks in the MPGA;
• wherein each of said FPGA and MPGA further comprises an exact layout of one or more pass-gate devices to couple said one or more logic blocks to said portion of interconnect wires, wherein:
• in the FPGA, a pass-gate device couples a logic block to an interconnect wire, said pass-gate device controlled by an output of a RAM bit, said RAM bit comprising:
• a logic one to couple the logic block to the interconnect wire;
• and
• a logic zero to decouple the logic block from the interconnect wire;
• and
• in the MPGA, said pass-gate device is decoupled from said interconnect wire when the RAM bit comprises a logic zero;
• and
• in the MPGA, said pass-gate device is replaced by a metal jumper when the RAM bit comprises a logic one;
• and
• wherein an interconnect wire in the FPGA comprises a high capacitance due to the pass-gate device junctions coupled to the interconnect wire, and wherein said interconnect wire in the MPGA comprises less capacitance due to the pass-gate junctions decoupled from the interconnect wire;
• and
• an interconnect wire coupled to a logic block encounters a high resistance from the on pass-gate device in the FPGA, and wherein said interconnect wire coupled to the logic block in the MPGA encounters less resistance from the metal-jumper.

A computer implemented method of converting designs from a field programmable gate array (FPGA) to a mask programmable gate array (MPGA), comprising:

• generating a bit-stream of memory data to program an FPGA comprising a programmable logic block array, a plurality of programmable interconnect wires;
• and
• converting the bit-steam to a custom metal pattern to mask program an MPGA comprising identical layouts of the programmable logic block array and the plurality of programmable interconnect wires,
• wherein each of said FPGA and MPGA devices comprises an exact layout of a portion of interconnect wires to couple one or more of said logic blocks;
• and
• in said bit stream to configure the FPGA, a second portion of bits determine the interconnect wire coupling of said one or more logic blocks in the FPGA;
• and
• said conductive pattern to configure the MPGA, wherein the result of said second portion of bits in the FPGA is replicated in the second portion of the conductive pattern to provide identical interconnect wire coupling of said one or more logic blocks in the MPGA;
• wherein each of said FPGA and MPGA further comprises an exact layout of one or more pass-gate devices to couple said one or more logic blocks to said portion of interconnect wires, wherein:
• in the FPGA, a pass-gate device couples a logic block to an interconnect wire, said pass-gate device controlled by an output of a RAM bit, said RAM bit comprising:
• a logic one to couple the logic block to the interconnect wire;
• and
• a logic zero to decouple the logic block from the interconnect wire;
• and
• in the MPGA, said pass-gate device is decoupled from said interconnect wire when the RAM bit comprises a logic zero;
• and
• in the MPGA, said pass-gate device is replaced by a metal jumper when the RAM bit comprises a logic one;
• and
• wherein an interconnect wire in the FPGA comprises a high capacitance due to the pass-gate device junctions coupled to the interconnect wire, and wherein said interconnect wire in the MPGA comprises less capacitance due to the pass-gate junctions decoupled from the interconnect wire;
• and
• an interconnect wire coupled to a logic block encounters a high resistance from the on pass-gate device in the FPGA, and wherein said interconnect wire coupled to the logic block in the MPGA encounters less resistance from the metal-jumper.