US 7,627,840 B2 · Method for soft error modeling with double current pulse

Abstract

A method of modeling soft errors in a logic circuit uses two separate current sources inserted at the source and drain of a device to simulate a single event upset (SEU) caused by, e.g., an alpha-particle strike. In an nfet implementation the current flows from the source or drain toward the body of the device. Current waveforms having known amplitudes are injected at the current sources while simulating operation of the logic circuit and the state of the logic circuit is determined from the simulated operation. The amplitudes of the current waveforms can be independently adjusted. The simulator monitors the state of device and makes a log entry when a transition occurs. The process may be repeated for other devices in the logic circuit to provide an overall characterization of the susceptibility of the circuit to soft errors.

Claims20

Dependent claims

A method of modeling a soft error in a logic circuit, comprising:

providing a circuit description for the logic circuit wherein the circuit description includes at least one device having a source terminal, a drain terminal, a gate terminal and a body;
inserting in the circuit description a first current source at the source terminal and a second current source at the drain terminal wherein the first and second current sources direct current in opposing directions with respect to the body;
simulating operation of the logic circuit while injecting a first current waveform at the first current source and injecting a second current waveform at the second current source, wherein the first and second current waveforms have different amplitudes based on a ratio of drain and source resistances of the device;
and
determining a state of the logic circuit from the simulated operation.

2 more elements

A computer system comprising:

one or more processors which process program instructions;
a memory device connected to said one or more processors;
and
program instructions residing in said memory device which when executed by said one or more processors perform the method for modeling a soft error in a logic circuit by providing a circuit description for the logic circuit wherein the circuit description includes at least one device having a source terminal, a drain terminal, a gate terminal and a body, inserting in the circuit description a first current source at the source terminal and a second current source at the drain terminal wherein the first and second current sources direct current in opposing directions with respect to the body, simulating operation of the logic circuit while injecting a first current waveform at the first current source, and injecting a second current waveform at the second current source wherein the first and second current waveforms have different amplitudes based on a ratio of drain and source resistances of the device, and determining a state of the logic circuit from the simulated operation.

1 more element

A computer program product comprising:

a computer-readable medium;
and
program instructions residing in said medium which when executed by a computer perform the method for modeling a soft error in a logic circuit by providing a circuit description for the logic circuit wherein the circuit description includes at least one device having a source terminal, a drain terminal, a gate terminal and a body, inserting in the circuit description a first current source at the source terminal and a second current source at the drain terminal wherein the first and second current sources direct current in opposing directions with respect to the body, simulating operation of the logic circuit while injecting a first current waveform at the first current source and injecting a second current waveform at the second current source, wherein the first and second current waveforms have different amplitudes based on a ratio of drain and source resistances of the device, and determining a state of the logic circuit from the simulated operation.

Dependencies are inferred from the claim text.

Method for soft error modeling with double current pulse

Life of this patent

Method for soft error modeling with double current pulse

Life of this patent

Abstract

Claims20