Monitoring a data processor to detect abnormal operation
AssigneeArm Limited
InventorsChristopher Pedley, Jonathan Sean Callan, Hedley James Francis
Life of this patent
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Abstract
Monitoring logic 20 for monitoring a data processor 10 to detect if it is not operating as anticipated, the monitoring logic 20 comprising: a timer 27 operable to measure a predetermined time; detection logic 24; and control logic 22; wherein said detection logic is operable to detect a data or instruction access to at least one predetermined address and in response to not detecting said data or instruction access within said predetermined time, said control logic is operable to send a control signal to said data processor, said control signal controlling said data processor to perform a predetermined operation.
Claims16
Monitoring logic for monitoring a data processor to detect if it is not operating as anticipated, said monitoring logic comprising:
- a timer for measuring a predetermined time;
- detection logic for detecting a data or instruction access to at least one predetermined address;
- and
- control logic, responsive to said detection logic not detecting said data or instruction access within said predetermined time, configured for sending a control signal to said data processor, said control signal controlling said data processor to perform a predetermined operation, wherein said predetermined operation comprises switching to a predetermined address for storing a crash handling routine for addressing a problem without resetting said data processor.
A method of monitoring a data processor to detect if it is not operating as anticipated, said method comprising the steps of:
- (i) starting the measurement of a predetermined time;
- (ii) monitoring a data or instruction access to at least one predetermined address;
- and either
- (iii) detecting a data or instruction access and returning to step (i);
- or
- (iii) in response to not having detected said data or instruction access within said predetermined time, controlling said data processor to perform a predetermined operation, wherein said predetermined operation comprises switching to a predetermined address for storing a crash handling routine for addressing a problem without resetting said data processor.
Monitoring means for monitoring a data processor to detect if it is not operating as anticipated, said monitoring means comprising:
- timing means for measuring a predetermined time;
- detection means for detecting a data or instruction access to at least one predetermined address;
- and
- control means for controlling said data processor to perform a predetermined operation;
- wherein
- said control means, is responsive to said detection means not detecting said data or instruction access within said predetermined time, for sending a control signal to said data processor, said control signal controlling said data processor to perform said predetermined operation, wherein said predetermined operation comprises switching to a predetermined address for storing a crash handling routine for addressing a problem without resetting said data processor.
Dependencies are inferred from the claim text.