Integrated hard-wired or partly hard-wired CRC generation and/or checking architecture for a physical coding sublayer in a programmable logic device
AssigneeAltera Corporation
InventorsDivya Vijayaraghavan, Michael Menghui Zheng, Chong H. Lee, Ning Xue, Tam Nguyen
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Abstract
A programmable logic integrated circuit device (“PLD”) includes high-speed serial interface (“HSSI”) circuitry that is at least partly hard-wired to perform at least some functional aspects of the HSSI operations. Cyclic redundancy check (CRC) generation and/or checking circuitry is now included in this HSSI circuitry, and again, this CRC circuitry is at least partly hard-wired to perform at least some functional aspects of its operations(s).
Claims23
A programmable logic device comprising:
- PLD core circuitry;
- receiver circuitry for receiving a serial data signal and converting it to successive parallel words of data that form part of a packet of data;
- and
- CRC checking circuitry for performing a CRC checking operation on the packet and reporting results of that operation to the PLD core circuitry, the CRC checking circuitry also applying the packet to the PLD core circuitry, and the CRC checking circuitry being at least partly hard-wired for performance of at least some functional aspects of the CRC checking operation.
A programmable logic device comprising:
- PLD core circuitry for outputting parallel data words that form part of a packet of data;
- CRC generation circuitry for performing a CRC generation operation on the part of the packet and adding the results of that operation to the packet, the CRC generation circuitry being at least partly hard-wired for performance of at least some functional aspects of the CRC generation operation;
- and
- transmitter circuitry for converting data from the packet to a serial data signal for transmission from the device.
A programmable logic device comprising:
- programmable logic circuitry;
- and
- at least partly hard-wired circuitry, the at least partly hard-wired circuitry including:
- CRC generation circuitry for performing a CRC operation on data from the programmable logic circuitry and for adding results of that operation to the data to produce a packet of data;
- and
- transmitter circuitry for converting data from the packet to a serial data signal for transmission from the device.
Dependencies are inferred from the claim text.