Memory device with speculative commands to memory core
AssigneeIntel Corporation
InventorKuljit S. Bains
Life of this patent
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Abstract
In some embodiments, a chip includes a memory core, error detection circuitry, and a control unit. The error detection circuitry determines the validity of error detection signals associated with speculative and non-speculative commands received by the chip and to provide validity signals indicative of the determined validity. The control unit provides the speculative commands to the memory core to be acted on before the control unit receives the associated validity signals and to provide the non-speculative commands to the memory core to be acted on only after receiving associated validity signals that indicate the associated error detection signals are valid. Other embodiments are described and claimed.
Claims23
A chip comprising:
- a memory core;
- error detection circuitry to determine the validity of error detection signals associated with speculative and non-speculative commands received by the chip and to provide validity signals indicative of the determined validity;
- and
- a control unit to provide the speculative commands to the memory core to be acted on before the control unit receives the associated validity signals and to provide the non-speculative commands to the memory core to be acted on only after receiving associated validity signals that indicate the associated error detection signals are valid.
A system comprising:
- a first chip including:
- (a) a memory core;
- (b) error detection circuitry to determine the validity of error detection signals associated with speculative and non-speculative commands received by the chip and to provide validity signals indicative of the determined validity;
- and
- (c) a control unit to provide the speculative commands to the memory core to be acted on before the control unit receives the associated validity signals and to provide the non-speculative commands to the memory core to be acted on only after receiving associated validity signals that indicate the associated error detection signals are valid;
- a second chip coupled to the first chip, wherein the second chip includes:
- (a) scheduling circuitry to schedule commands to be provided to the first chip;
- (b) receivers to signals from the first chip indicating the groups of data including the speculative commands were determined to have invalid error detection signals in the first chip;
- and
- (c) a error handling unit to receive signals in response to detection of the error alert signals and to respond thereto.
Dependencies are inferred from the claim text.